Renesas H8S/2111B - Manual (Page 315)

Rev. 1.00, 05/04, page 281 of 544
13.3 Register Descriptions
The I 2 C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see
section 3.2.3, Serial Timer Control Register (STCR).
• I 2 C bus data register (ICDR)
• Slave address register (SAR)
• Second slave address register (SARX)
• I
2 C bus mode register (ICMR)
• I 2 C bus control register (ICCR)
• I 2 C bus status register (ICSR)
• DDC switch register (DDCSWR)* 1
• I 2 C bus extended control register (ICXR)
• Port G control register (PGCTL)* 2
Notes: 1. DDCSWR is available only for IIC_0.
2. PGCTL register is common to IIC_0 and IIC_1.