Maxim Integrated MAX3420E - Manual (Page 6)

device address and the armed endpoint sends the FIFO data to the host.
4. What if a USB IN request comes in while firmware is loading the IN FIFO?
The MAX3420E takes care of this. It automatically answers an IN request to an "unarmed" IN
FIFO with a NAK (Negative Acknowledge) handshake. This handshake instructs the USB host
that the endpoint is busy, and that the host should try later with another IN request.
5. How do I know when to load an IN FIFO?
The MAX3420E provides interrupt request bits for the IN endpoints called IN3BAVIRQ,
IN2BAVIRQ, and IN0BAVIRQ, where "BAV" indicates "Buffer Available". The MAX3420E logic
sets an IN endpoint BAVIRQ bit after a device reset, or when IN FIFO data has been
successfully transferred and acknowledged by the host. At power-on, the BAVIRQ bits are set
to indicate that the IN FIFOS are initially available for loading. These are the only register bits
that are set to 1 by a reset—all the rest are set to 0.
6. What if there is a USB transfer error? Do I need to write code to handle the error
condition?
No. The MAX3420E manages this for you. If the MAX3420E receives an error condition back
from the host, it automatically resends the same data when the host retries the IN transfer.
The MAX3420E also automatically handles other error checking such as data toggles. Some
possible USB errors (such as a user unplugging the cable in the middle of a data transfer)
need to be handled by firmware.
7. How do I program a BULK OUT transfer?
When the host sends OUT data, the MAX3420E stores the bytes in an OUT endpoint FIFO.
After the transfer is complete and verified to be error-free, the MAX3420E asserts a "DAV"
(Data Available) interrupt request bit for the particular endpoint. This alerts the SPI controller to
read the FIFO bytes. The SPI controller first reads an OUT FIFO byte-count register to
determine how many bytes in the 64 byte FIFO are valid. It then reads that number of bytes
by repeated reads to the OUTFIFO register. Finally, the SPI controller clears the OUT DAV
IRQ bit (by writing 1 to it) to "rearm" the endpoint for another OUT transfer.
8. How about INTERRUPT transfers?
Interrupt transfers are programmed identically to BULK transfers. They differ only in how they
are described in the device descriptors sent back to the host during enumeration.
9. How do I program a SETUP transfer?
The USB host uses a CONTROL transfer to send a SETUP packet to the MAX3420E along
with eight bytes that serve as a USB "op-code". The MAX3420E stores these bytes in an 8-
byte FIFO, and then asserts a Setup Data Available interrupt request. The SPI master
responds by reading the eight SETUP bytes at register address R4 (SUDFIFO), interpreting
the USB request from these bytes, and taking the appropriate action. When finished servicing
the request, the USPI master sets a bit called ACKSTAT (ACK from acknowledge, STAT from
STATUS stage) to tell the MAX3420E to acknowledge the status stage of the CONTROL
transfer.
10. Do I need to program the USB data toggles?
No. The MAX3420E handles these toggles automatically during USB transfers. The only time
firmware might need to intervene is when the host sets a new configuration in a
multiconfiguration design (these are rare). The MAX3420E has register bits to clear the
endpoint toggles for this purpose.
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