Maxim Integrated DS33Z41 - Manual (Page 13)

DS33Z41 Quad IMUX Ethernet Mapper
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5 MAJOR OPERATING MODES
Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link
aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information
on microprocessor control is available in Section
8.1 .
6 BLOCK DIAGRAMS
Figure 6-1. Detailed Block Diagram
MAC
RMII
MII
SDRAM
Interface
Buffer Dev
Div by 2,4,12
Output Clocks
25,50
Mhz
100 Mhz Oscillator
SYSCLKI
SDCLKO
Buffer
Div by 1,2,4,8,10
Output clocks:
50,25 Mhz,2.5 Mhz
50 or 25 Mhz Oscillator
TX_CLK1
RX_CLK1
TCLKI1
RCLKI1
REF_CLKO
50 or 25 Mhz
MDC
REF_CLK
SDRAM
HDLC
+
Serial
Interface
CIR
Line 1
Arbiter
X.86
TSER
RSER
RXD
TXD
Microport
JTAG
IMUX