Maxim Integrated DS33Z41 - Manual (Page 18)

DS33Z41 Quad IMUX Ethernet Mapper
18 of 167
NAME PIN TYPE FUNCTION
SDRAM CONTROLLER
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
SDATA[4]
SDATA[5]
SDATA[6]
SDATA[7]
SDATA[8]
SDATA[9]
SDATA[10]
SDATA[11]
SDATA[12]
SDATA[13]
SDATA[14]
SDATA[15]
SDATA[16]
SDATA[17]
SDATA[18]
SDATA[19]
SDATA[20]
SDATA[21]
SDATA[22]
SDATA[23]
SDATA[24]
SDATA[25]
SDATA[26]
SDATA[27]
SDATA[28]
SDATA[29]
SDATA[30]
SDATA[31]
M1
L2
N1
M2
N2
N4
N3
L4
J3
M3
H3
J1
J2
K1
K2
L1
M12
H11
M11
N13
N11
L13
N12
K13
J13
J12
H13
H12
G12
F11
G11
L10
IOZ
SDRAM Data Bus Bits 0 to 31: The 32 pins of the SDRAM data bus
are inputs for read operations and outputs for write operations. At all
other times, these pins are high impedance.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SDA[0]
SDA[1]
SDA[2]
SDA[3]
SDA[4]
SDA[5]
SDA[6]
SDA[7]
SDA[8]
SDA[9]
SDA[10]
SDA[11]
N9
N10
L11
K11
L7
L8
L9
L5
M5
M7
M8
N8
O
SDRAM Address Bus 0 to 11. The 12 pins of the SDRAM address bus
output the row address first, followed by the column address. The row
address is determined by SDA0 to SDA11 at the rising edge of clock.
Column address is determined by SDA0-SDA9 and SDA11 at the rising
edge of the clock. SDA10 is used as an auto-precharge signal.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SBA[0]
SBA[1] M6
N7
I
SDRAM Bank Select. These 2 bits select 1 of 4 banks for the
read/write/precharge operations.
Note: All SDRAM operations are controlled entirely by the DS33Z41.
No user programming for SDRAM buffering is required.
SRAS K6 O
SDRAM Row Address Strobe. Active-low output, used to latch the row
address on rising edge of SDCLKO. It is used with commands for Bank
Activate, Precharge, and Mode Register Write.