Motorola MPC8260 - Manual (Page 719)

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-23
Part IV. Communications Processor Module
Figure 26-11. Synchronization with SMSYNx
If both SMCMR[REN] and SMCMR[TEN] are set, the Þrst falling edge of SMSYN causes
both the transmitter and receiver to achieve synchronization. The SMC transmitter can be
disabled and reenabled and SMSYN can be used again to resynchronize the transmitter
itself. Section 26.2.4, ÒDisabling SMCs On-the-Fly,Ó describes how to safely disable and
reenable the SMC. Simply clearing and setting TEN may be insufÞcient. The receiver can
also be resynchronized this way.
26.4.5 Using the Time-Slot Assigner (TSA) for Synchronization
The TSA offers an alternative to using SMSYN to internally synchronize the SMC channel.
This method is similar, except that the synchronization event is the Þrst time-slot for this
SMC receiver/transmitter after the frame sync indication rather than the falling edge of
SMSYN. Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes how to
conÞgure time slots. The TSA allows the SMC receiver and transmitter to be enabled
simultaneously and synchronized separately; SMSYN does not provide this capability.
Figure 26-12 shows synchronization using the TSA.
SMCLK
SMSYN
SMTXD 1s are sent Five 1s are sent
TEN set
here
Tx FIFO
loaded
approximately
here
Five 1s
assume
character
length
equals 5
First bit of
first 5-bit
transmit
character
(lsb)
Transmission
could begin
here if Tx FIFO
not loaded
in time
SMSYN
detected
low here
SMCLK
SMSYN
SMRXD
REN set
here or
First bit
of receive
data
(lsb)
SMSYN
detected
low here
ENTER HUNT
MODE
command
issued
NOTES:
SMCLK is an internal clock derived from an external
CLKx or a baud rate generator. 1.
This example shows the SMC receiver and transmitter 2.
enabled separately. If the REN and TEN bits were set at
the same time, a single falling edge of SMSYN would
synchronize both.
SMC1 Transmit Data
SMC1 Receive Data