Motorola MVME197LE - Manual (Page 62)

Functional Description
4-4 User’s Manual
4
BOOT ROM
Currently a socket (socket will be removed from module in later board
revisions) for a 32-pin PLCC/CLCC ROM/EPROM referred to as BOOT ROM
or DROM (Download ROM) is provided. It is organized as a 128K x 8 device,
but as viewed from the processor it looks like a 16K x 64 memory. This
memory is mapped starting at location $FFF80000, but after a local reset it is
also mapped at location 0, providing a reset vector and bootstrap code for the
processor. The DR0 bit in the General Control Register (GCR) of the PCCchip2
must be cleared to disable the BOOT ROM memory map at 0.
FLASH Memory
Up to 1MB of FLASH memory is available on the board. FLASH memory
works like EPROM, but can be erased and reprogrammed by software. It is
organized as 32 bits wide, but to the processor it looks as 64 bits wide. It is
mapped at location $FF800000. Reads can be of any size, including burst
transfers, but writes are always 32 bits wide, regardless of the size specified for
the transfer. For this reason, software should only use 32-bit write transfers.
This memory is controlled by the BusSwitch, and the memory size, access
time, and write enable capability can be programmed via the ROM Control
Register (ROMCR) in the BusSwitch. The FLASH memory can be accessed
from the processor bus only. It is not accessible from the local peripheral bus
or VMEbus.
Onboard DRAM
The MVME197LE onboard DRAM (2 banks of 32MB memory, one optionally
installed) is sized at 32MB using 1M x 4 devices and configured as 256 bits
wide. The DRAM is four-way interleaved to efficiently support cache burst
cycles. The DRAM is controlled by the DCAM and ECDM, and the map
decoders in the DCAM can be programmed through the I
2
Cbus interface in the
ECDM to accommodate different base address(es) and sizes. The onboard
DRAM is not reset by a local peripheral bus reset. Refer to the DCAM and
ECDM chapters in the MVME197LE, MVME197DP, and MVME197SP Single
Board Computers Programmer’s Reference Guide for detailed programming
information.
Battery Backup RAM and Clock
The MK48T08 RAM and clock chip is used on the MVME197LE. This chip
provides a time of day clock, oscillator, crystal, power fail detection, memory
write protection, 8KB of RAM, and a battery in one 28-pin package. The clock
provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour