Marantz MAR770 - Manual (Page 19)

17
8.1.2 Test instructions
Supply voltages
The display board receives several voltages via connector
JY01.
•
VFTD : -35V ±5% measured at pin 2 of conn. JY01.
• VDC1-VDC2 : 3V8 ±10% measured between pin 1 and 3 of
conn. 1119.
• +5V : +5V ±5% measured at pin 10 of conn. JY01
Voltages VFTD, VDC1 and VDC2 are produced in the power
supply unit and sent to the display board via the CDR main
board. The +5V voltage is produced on the CDR main board as
D5V.
Clock signal
As clock driver for the display controller, a resonator of 8 MHz
(XY01) is used. The signal can be measured at pins 8 and 9 of
the display controller : 8 MHz ±5%.
Control signals
RESET
The reset signal comes via pin 4 of conn. JY01 from the DASP
master processor on the CDR main board (SYS_RESET). The
reset is low active. It should be kept low during power up for at
least 3 machine cycles with supply voltage in operating range
and a stable clock signal (1 machine cycle = 12 x 1/Fc (8 MHz)
sec.). During normal operation, the reset should be high (3V3).
The high signal is 3V3 because the DASP operates on 3V3.
I2C DATA/I2C CLK
These lines connect to the DASP master processor via
respectively pin 5 and pin 7 of conn. JY01
. When there is no
communication, they should have the high level (+5V). The
oscillogram below gives an indication of how these signals
should look like.
Figure 8-2 ‘I2C signals’
FTD drive lines
Filament voltage
Should measure 3.8V ±10% (=VDC1-VDC2) between pins 1-3
and pins
1-52 of the FTD(VX01).
Grid lines
Level and timing of all grid lines, G1-->G15, can be checked
either at the FTD itself or at the display controller. Grid lines
G13, G14 and G15 each have an extra current amplifier in line
: QY02 for G13, QY03 for G14 and QY04 for G15.
A typical
grid line signal shows in the oscillogram below.
Figure 8-3 ‘Gridline’
Segment lines
Level and timing of all segment lines, P1-->P21, can be
checked either at the FTD itself or at the display controller.
The data on these segment lines however,
characters displayed. The oscillogram below shows a
segment line with data. A segment line without data
maintains a -38V level.
Figure 8-4 ‘Segment line’
Key matrix lines
The lines connected to pins 34, 35, 36 and 37 of the display
controller act as matrix scanners. Without a key pressed, they
maintain a low level. As soon as a key is pressed, the scanning
line connected to that key puts out a scanning signal, which
should look like the oscillogram below. This scanning signal
goes via the pressed key to I/O port 4 of the display controller
(pins 28 to 33). The display controller can now determine which
key has been pressed. Without a key pressed, pins 28 to 33 of
the display controller maintain a high level (+5V).
PM33 92A
CH1! 2. 00 V =
CH2 2 V= M TB10.0m s
ch 1+
+5V
0V
+5V
0V
I2C DATA
I2C CLK
CL 96532076_025.eps
290799
PM3392A
CH1! 10.0 V= M TB1. 00ms ch 1+
0V
+4V
-38V
CL 96532076_024.eps
290799
PM33 92A
CH1! 10 .0 V= M TB1. 00ms ch 1+
0V
+5V
-35V
CL 96532076_027.eps
290799
depends on the