Maxim Integrated DS33R11 - Manual (Page 5)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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12.4 E1 M ODE .................................................................................................................................... 308
13 OPERATING PARAMETERS ........................................................................................................ 313
13.1 T HERMAL C HARACTERISTICS ....................................................................................................... 314
13.2 MII I NTERFACE ............................................................................................................................ 315
13.3 RMII I NTERFACE ......................................................................................................................... 317
13.4 MDIO I NTERFACE ....................................................................................................................... 319
13.5 T RANSMIT WAN I NTERFACE ........................................................................................................ 320
13.6 R ECEIVE WAN I NTERFACE .......................................................................................................... 321
13.7 SDRAM T IMING .......................................................................................................................... 322
13.8 M ICROPROCESSOR B US AC C HARACTERISTICS ........................................................................... 324
13.9 AC C HARACTERISTICS : R ECEIVE -S IDE ........................................................................................ 327
13.10 AC C HARACTERISTICS : B ACKPLANE C LOCK T IMING ..................................................................... 331
13.11 AC C HARACTERISTICS : T RANSMIT S IDE ....................................................................................... 332
13.12 JTAG I NTERFACE T IMING ............................................................................................................ 335
14 JTAG INFORMATION .................................................................................................................... 336
14.1 JTAG TAP C ONTROLLER S TATE M ACHINE D ESCRIPTION ............................................................. 337
14.2 I NSTRUCTION R EGISTER .............................................................................................................. 339
14.3 JTAG ID C ODES ......................................................................................................................... 341
14.4 T EST R EGISTERS ........................................................................................................................ 341
14.4.1 Boundary Scan Register .....................................................................................................................341
14.4.2 Bypass Register ..................................................................................................................................341
14.4.3 Identification Register .........................................................................................................................341
14.5 JTAG F UNCTIONAL T IMING ......................................................................................................... 342
15 PACKAGE INFORMATION............................................................................................................ 343
15.1 P ACKAGE O UTLINE D RAWING OF 256-BGA (V IEW FROM B OTTOM OF D EVICE ).............................. 343
16 DOCUMENT REVISION HISTORY ................................................................................................ 344