Table 5-2 – IBM POWERPC 750GL User Manual
Page 188
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 188 of 377
gx_05.fm.(1.2)
March 27, 2006
The no-execute option provided in the segment register lets the operating system program determine
whether instructions can be fetched from an area of memory. The remaining options are enforced based on a
combination of information in the segment descriptor and the page table entry. Thus, the supervisor-only
option allows only read and write operations generated while the processor is operating in supervisor mode
(MSR[PR] = 0) to access the page. User accesses that map into a supervisor-only page cause an exception.
Finally, a facility in the virtual environment architecture (VEA) and the operating environment architecture
(OEA) allows pages or blocks to be designated as guarded, preventing out-of-order accesses that might
cause undesired side effects. For example, areas of the memory map used to control I/O devices can be
marked as guarded so accesses do not occur unless they are explicitly required by the program.
For more information on memory protection, see “Memory Protection Facilities,” in Chapter 7, “Memory
Management,” in the PowerPC Microprocessor Family: The Programming Environments Manual.
5.1.5 Page History Information
The MMUs of PowerPC processors also define referenced (R) and changed (C) bits in the page-address-
translation mechanism that can be used as history information relevant to the page. The operating system
can use these bits to determine which areas of memory to write back to disk when new pages must be allo-
cated in main memory. While these bits are initially programmed by the operating system into the page table,
the architecture specifies that they can be maintained either by the processor hardware (automatically) or by
some software-assist mechanism.
Implementation Note: When loading the TLB, the 750GX checks the state of the changed and referenced
bits for the matched PTE. If the referenced bit is not set and the table-search operation is initially caused by a
load operation or by an instruction fetch, then the 750GX automatically sets the referenced bit in the transla-
tion table. Similarly, if the table-search operation is caused by a store operation and either the referenced bit
or the changed bit is not set, then the hardware automatically sets both bits in the translation table. In addi-
tion, when the address translation of a store operation hits in the DTLB, the 750GX checks the state of the
changed bit. If the bit is not already set, the hardware automatically updates the DTLB and the translation
table in memory to set the changed bit. For more information, see Section 5.4.1, Page History Recording, on
page 196.
Table 5-2. Access Protection Options for Pages
Option
User Read
User Write
Supervisor Read
Supervisor Write
I-Fetch
Data
I-Fetch
Data
Supervisor-only
V
V
V
A
A
A
Supervisor-only-no-execute
V
V
V
V
A
A
Supervisor-write-only
A
A
V
A
A
A
Supervisor-write-only-no-execute
V
A
V
V
A
A
Both (user/supervisor)
A
A
A
A
A
A
Both (user-/supervisor) no-execute
V
A
A
V
A
A
Both (user-/supervisor) read-only
A
A
V
A
A
V
Both (user/supervisor) read-only-no-execute
V
A
V
V
A
V
A Access
permitted
V Protection
violation