Document Outline

• Contents
  • Unpacking and Special Handling Instructions
  • Revision History
  • Three Year Limited Warranty
  • 1.0 ICP-CM CPU
  • 1.01 Interfacing
  • 1.02 Peripherals
  • 1.03 Software
  • 1.04 Graphics
  • 1.1 Specifications
  • 1.2 Functional Overview
  • Figure 1.20 ICP-CM Interfacing
  • Figure 1.21 ICP-CM Board Overview
  • 1.3 Software
  • 1.31 Windows XP (Professional / Embedded)
  • 1.32 Windows 2000 (Professional)
  • 1.33 Linux
  • 1.34 VentureCom
  • 1.35 Windows CE
  • 1.36 VxWorks
  • 1.37 OS-9 x86
  • 1.38 QNX
  • 1.39 Jbed
  • 1.4 Hardware
  • 1.41 Block Diagram
  • Figure 1.41 Block Diagram
  • 1.42 Connector Location
  • Figure 1.42 Connector Locations
  • 1.43 Connector Description
  • Table 1.43 Connector Description
  • Table 1.43 Continued
  • 1.44 Front-Panel Features
  • Table 1.44 Front Panels
  • Figure 1.44 Front-Panel Options
  • 1.45 Interface Positions
  • Figure 1.45 Interfaces
  • 1.46 Construction - 4HP Standard CPU
  • Figure 1.46 Construction of CPU with Heat-Sink Assembly
  • 1.47 Construction - 8HP Standard CPU
  • Figure 1.47 Construction of CPU with Heat-Sink Assembly
  • 1.48 Construction - 8HP Standard CPU with AGP
  • Figure 1.48 Construction of CPU with Heat-Sink Assembly
  • 1.49 Power Requirements
  • Table 1.49 ICP-CM Power Reqirements
  • 1.50 Power Consumption
  • Figure 1.50 ICP-CM Power Consumption
  • 1.51 Thermal Considerations
  • Table 1.51 ICP-CM Airflow Requirements
  • 2.0 Memory Map
  • Figure 2.00 System Architecture
  • 2.1 I/O Mapped Peripherals
  • Table 2.10 Legacy I/O Map (ISA Compatible)
  • Table 2.10 Legacy I/O Map (ISA Compatible) Contd.
  • 2.2 Memory Mapped Peripherals
  • 2.3 Interrupt Routing
  • Table 2.30 PC-AT Interrupt Definitions
  • 2.4 DMA Channel Descriptions
  • Table 2.40 DMA Channel Description
  • 2.5 Inova CM SMB Devices
  • Table 2.50 SMB Devices
  • 2.6 Inova CM PCI Device List
  • Table 2.60 Legacy I/O Map (ISA Compatible)
  • 2.7 Interrupt Configuration
  • Table 2.70 CompactPCI Bus Interrupts
  • 2.8 Timer / Counter
  • 2.9 Watchdog
  • 3.0 CompactPCI J1/J2 Connectors
  • 3.01 CompactPCI Connector Naming
  • Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification
  • 3.02 CompactPCI J1 Connector
  • Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector
  • 3.03 ICP-PM Connector J1 and J2
  • Table 3.03 32-Bit CompactPCI J1 Pin Assignment
  • Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. with Rear I/O (D))
  • Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd.
  • Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration
  • 3.1 CompactPCI Backplane
  • Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot
  • 3.2 Interfaces
  • 3.21 J6 & J7 Ethernet
  • Figure 3.21 RJ45 Pinout
  • Table 3.21 Ethernet Standards & Connector Signals
  • 3.22 J17 VGA Interface
  • 3.23 Graphic Features (Chipset)
  • Table 3.23a highlights just some of the features of the standard integrated video controller.
  • Figure 3.23 High-Density D-Sub VGA Interface Pinout
  • Table 3.23b Video Output Connector Signals
  • 3.24 J19 USB Interface
  • Figure 3.24 USB Interface Pinout
  • Table 3.24 USB Connector Signals
  • 3.25 J10 Hot-Swap Interface
  • 3.26 SW1 Reset Button
  • 3.27 J9 CompactFlash Interface
  • 3.28 Connecting the CM to the Inova ICP-HD3(-ND)
  • 3.29 Connecting the CM to the Inova IPB-FPE12
  • 3.30 Connecting the CM to a Slim-Line Floppy-Disk
  • A1 ICP-HD-3(-ND) CPU Extension
  • A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP)
  • Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels
  • A1.2 IDE Carrier Board ICP-HD-3(-ND)
  • Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module
  • Table A1.2 Interface Description of the ICP-HD-3(-ND) Module
  • A2 ICP-HD-3(-ND) Interfaces
  • A2.1 COM1 & COM2 Interfaces
  • Figure A2.1 COM1 & COM2 Interface Pinout
  • Table A2.1 COM1 & COM2 Connector Signals
  • A2.2 Mouse & Keyboard Interfaces
  • Figure A2.2 Mouse & Keyboard Interface Pinout
  • Table A2.2 Mouse & Keyboard Connector Signals
  • Table A2.3 USB Connector Signals
  • A2.3 USB 2.0 Interfaces
  • Figure A2.3 USB Interface Pinout
  • A2.4 EIDE Interface
  • A2.5 Slim-Line Floppy Disk Interface
  • B1 IPB-FPE12 CPU Extension
  • B1.1 J13 Interface for LPT1
  • B1.2 IPB-FPE12 Front-Panel (4HP or 12HP)
  • Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU
  • B1.3 LPT1 Piggyback
  • Figure B1.3 LPT1 Piggyback Board IPB-FPE12
  • Table B1.3 IPB-FPE12 Connector Description
  • B1.4 LPT1 Interface
  • Figure B1.4 LPT1 Interface Pinout
  • Table B1.4 LPT1 Connector Signals
  • C1 ITM-RIO CPU Extension
  • C1.1 ITM-RIO-D Configurations
  • Table C1.10 Valid Rear I/O Configurations
  • Table C1.11 Rear I/O Module Functionality
  • C1.2 ITM-RIO Rear-Panels (4HP or 8HP)
  • Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x
  • C1.3 ITM-RIO-D-x Transition Module
  • Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x
  • Table C1.3 ITM-RIO-D-x Connector Description
  • C1.4 COM1 & COM2 Interfaces
  • Figure C1.4 COM1 & COM2 Interface Pinout
  • Table C1.4 COM1 & COM2 Connector Signals
  • C1.5 LPT1 Interface
  • Figure C1.5 LPT1 Interface Pinout
  • Table C1.5 LPT1 Connector Signals
  • C1.6 Mouse & Keyboard Interfaces
  • Figure C1.6 Mouse & Keyboard Interface Pinout
  • Table C1.6 Mouse & Keyboard Connector Signals
  • C1.7 VGA Interface
  • Figure C1.7 VGA Interface Pinout
  • Table C1.7 Video Output Connector Signals
  • C1.8 Fast Ethernet Interface
  • Figure C1.8 Fast Ethernet Interface Pinout
  • Table C1.8 Fast Ethernet Connector Signals
  • C1.9 USB Interface (USB 4)
  • Figure C1.9 USB Interface Pinout
  • Table C1.9 USB Connector Signals
  • C1.10 EIDE Interface
  • C1.11 Slim-Line Floppy Disk Interface
  • C1.12 ITM-RIO(C&D)-FHLU Extension
  • Figure C1.12 ITM-RIO(C&D)-FHLU
  • D1 IPM-ATA CPU Extension
  • D1.1 rJ2 Interface
  • Figure D1.1a Dedicated IPM-ATA Backplane
  • D1.1 rJ2 Interfaces (Contd.)
  • Figure D1.1b The Complete Connection Picture
  • D1.2 IPM-ATA-HD
  • Figure D1.2 IPM-ATA-HD Board Layout
  • Table D1.2 IPM-ATA-HD Jumper Description (CF Socket)
  • D1.3 IPM-ATA-CF
  • Figure D1.3 IPM-ATA-CF Board Layout
  • Table D1.3 IPM-ATA-CF Jumper Description
  • D1.4 IPM-ATA-PCMCIA
  • Figure D1.4 IPM-ATA-PCMCIA Board Layout
  • Table D1.4 IPM-ATA-PCMCIA Jumper Description
  • D1.5 Device Compatibility
  • Table D1.5 Compatibility List
  • E1 AGP-R7000 CPU Extension
  • Table E1.00 AGP Piggyback Configurations
  • E1.1 Specifications
  • E1.2 J4 Interface
  • Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback
  • Table E1.20 J4 Pinout
  • Table E1.20 J4 Pinout - Contd.
  • E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces
  • Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK
  • Table E1.30 J3 & J5 Interface Pinout
  • E1.4 J1 Front-Panel VGA/TMDS Interface
  • Figure E1.40 Standard Front-Panel VGA/TMDS Interface
  • Table E1.40 J1 Standard Front-Panel VGA/TMDS Pinout
  • Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D
  • Table E1.42 J2 DIP Switch Settings - TFT (24Bit TTL/CMOS)
  • E1.5 Rear I/O VGA Interface
• Overview Contents
  • 1.0 ICP-CM CPU
  • 1.01 Interfacing
  • 1.02 Peripherals
  • 1.03 Software
  • 1.04 Graphics
  • 1.1 Specifications
  • 1.2 Functional Overview
  • Figure 1.20 ICP-CM Interfacing
  • Figure 1.21 ICP-CM Board Overview
  • 1.3 Software
  • 1.31 Windows XP (Professional / Embedded)
  • 1.32 Windows 2000 (Professional)
  • 1.33 Linux
  • 1.34 VentureCom
  • 1.35 Windows CE
  • 1.36 VxWorks
  • 1.37 OS-9 x86
  • 1.38 QNX
  • 1.39 Jbed
  • 1.4 Hardware
  • 1.41 Block Diagram
  • Figure 1.41 Block Diagram
  • 1.42 Connector Location
  • Figure 1.42 Connector Locations
  • 1.43 Connector Description
  • Table 1.43 Connector Description
  • Table 1.43 Continued
  • 1.44 Front-Panel Features
  • Table 1.44 Front Panels
  • Figure 1.44 Front-Panel Options
  • 1.45 Interface Positions
  • Figure 1.45 Interfaces
  • 1.46 Construction - 4HP Standard CPU
  • Figure 1.46 Construction of CPU with Heat-Sink Assembly
  • 1.47 Construction - 8HP Standard CPU
  • Figure 1.47 Construction of CPU with Heat-Sink Assembly
  • 1.48 Construction - 8HP Standard CPU with AGP
  • Figure 1.48 Construction of CPU with Heat-Sink Assembly
  • 1.49 Power Requirements
  • Table 1.49 ICP-CM Power Reqirements
  • 1.50 Power Consumption
  • Figure 1.50 ICP-CM Power Consumption
  • 1.51 Thermal Considerations
  • Table 1.51 ICP-CM Airflow Requirements
• Configuration Contents
  • 2.0 Memory Map
  • Figure 2.00 System Architecture
  • 2.1 I/O Mapped Peripherals
  • Table 2.10 Legacy I/O Map (ISA Compatible)
  • Table 2.10 Legacy I/O Map (ISA Compatible) Contd.
  • 2.2 Memory Mapped Peripherals
  • 2.3 Interrupt Routing
  • Table 2.30 PC-AT Interrupt Definitions
  • 2.4 DMA Channel Descriptions
  • Table 2.40 DMA Channel Description
  • 2.5 Inova CM SMB Devices
  • Table 2.50 SMB Devices
  • 2.6 Inova CM PCI Device List
  • Table 2.60 Legacy I/O Map (ISA Compatible)
  • 2.7 Interrupt Configuration
  • Table 2.70 CompactPCI Bus Interrupts
  • 2.8 Timer / Counter
  • 2.9 Watchdog
• Interfaces Contents
  • 3.0 CompactPCI J1/J2 Connectors
  • 3.01 CompactPCI Connector Naming
  • Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification
  • 3.02 CompactPCI J1 Connector
  • Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector
  • 3.03 ICP-PM Connector J1 and J2
  • Table 3.03 32-Bit CompactPCI J1 Pin Assignment
  • Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. with Rear I/O (D))
  • Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd.
  • Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration
  • 3.1 CompactPCI Backplane
  • Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot
  • 3.2 Interfaces
  • 3.21 J6 & J7 Ethernet
  • Figure 3.21 RJ45 Pinout
  • Table 3.21 Ethernet Standards & Connector Signals
  • 3.22 J17 VGA Interface
  • 3.23 Graphic Features (Chipset)
  • Table 3.23a highlights just some of the features of the standard integrated video controller.
  • Figure 3.23 High-Density D-Sub VGA Interface Pinout
  • Table 3.23b Video Output Connector Signals
  • 3.24 J19 USB Interface
  • Figure 3.24 USB Interface Pinout
  • Table 3.24 USB Connector Signals
  • 3.25 J10 Hot-Swap Interface
  • 3.26 SW1 Reset Button
  • 3.27 J9 CompactFlash Interface
  • 3.28 Connecting the CM to the Inova ICP-HD3(-ND)
  • 3.29 Connecting the CM to the Inova IPB-FPE12
  • 3.30 Connecting the CM to a Slim-Line Floppy-Disk
• ICP-HD-3 Contents
  • A1 ICP-HD-3(-ND) CPU Extension
  • A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP)
  • Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels
  • A1.2 IDE Carrier Board ICP-HD-3(-ND)
  • Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module
  • Table A1.2 Interface Description of the ICP-HD-3(-ND) Module
  • A2 ICP-HD-3(-ND) Interfaces
  • A2.1 COM1 & COM2 Interfaces
  • Figure A2.1 COM1 & COM2 Interface Pinout
  • Table A2.1 COM1 & COM2 Connector Signals
  • A2.2 Mouse & Keyboard Interfaces
  • Figure A2.2 Mouse & Keyboard Interface Pinout
  • Table A2.2 Mouse & Keyboard Connector Signals
  • Table A2.3 USB Connector Signals
  • A2.3 USB 2.0 Interfaces
  • Figure A2.3 USB Interface Pinout
  • A2.4 EIDE Interface
  • A2.5 Slim-Line Floppy Disk Interface
• IPB-FPE12 Contents
  • B1 IPB-FPE12 CPU Extension
  • B1.1 J13 Interface for LPT1
  • B1.2 IPB-FPE12 Front-Panel (4HP or 12HP)
  • Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU
  • B1.3 LPT1 Piggyback
  • Figure B1.3 LPT1 Piggyback Board IPB-FPE12
  • Table B1.3 IPB-FPE12 Connector Description
  • B1.4 LPT1 Interface
  • Figure B1.4 LPT1 Interface Pinout
  • Table B1.4 LPT1 Connector Signals
• ITM-RIO Contents
  • C1 ITM-RIO CPU Extension
  • C1.1 ITM-RIO-D Configurations
  • Table C1.10 Valid Rear I/O Configurations
  • Table C1.11 Rear I/O Module Functionality
  • C1.2 ITM-RIO Rear-Panels (4HP or 8HP)
  • Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x
  • C1.3 ITM-RIO-D-x Transition Module
  • Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x
  • Table C1.3 ITM-RIO-D-x Connector Description
  • C1.4 COM1 & COM2 Interfaces
  • Figure C1.4 COM1 & COM2 Interface Pinout
  • Table C1.4 COM1 & COM2 Connector Signals
  • C1.5 LPT1 Interface
  • Figure C1.5 LPT1 Interface Pinout
  • Table C1.5 LPT1 Connector Signals
  • C1.6 Mouse & Keyboard Interfaces
  • Figure C1.6 Mouse & Keyboard Interface Pinout
  • Table C1.6 Mouse & Keyboard Connector Signals
  • C1.7 VGA Interface
  • Figure C1.7 VGA Interface Pinout
  • Table C1.7 Video Output Connector Signals
  • C1.8 Fast Ethernet Interface
  • Figure C1.8 Fast Ethernet Interface Pinout
  • Table C1.8 Fast Ethernet Connector Signals
  • C1.9 USB Interface (USB 4)
  • Figure C1.9 USB Interface Pinout
  • Table C1.9 USB Connector Signals
  • C1.10 EIDE Interface
  • C1.11 Slim-Line Floppy Disk Interface
  • C1.12 ITM-RIO(C&D)-FHLU Extension
  • Figure C1.12 ITM-RIO(C&D)-FHLU
• IPM-ATA
  • D1 IPM-ATA CPU Extension
  • D1.1 rJ2 Interface
  • Figure D1.1a Dedicated IPM-ATA Backplane
  • D1.1 rJ2 Interfaces (Contd.)
  • Figure D1.1b The Complete Connection Picture
  • D1.2 IPM-ATA-HD
  • Figure D1.2 IPM-ATA-HD Board Layout
  • Table D1.2 IPM-ATA-HD Jumper Description (CF Socket)
  • D1.3 IPM-ATA-CF
  • Figure D1.3 IPM-ATA-CF Board Layout
  • Table D1.3 IPM-ATA-CF Jumper Description
  • D1.4 IPM-ATA-PCMCIA
  • Figure D1.4 IPM-ATA-PCMCIA Board Layout
  • Table D1.4 IPM-ATA-PCMCIA Jumper Description
  • D1.5 Device Compatibility
  • Table D1.5 Compatibility List
• AGP-R7000
  • E1 AGP-R7000 CPU Extension
  • Table E1.00 AGP Piggyback Configurations
  • E1.1 Specifications
  • E1.2 J4 Interface
  • Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback
  • Table E1.20 J4 Pinout
  • Table E1.20 J4 Pinout - Contd.
  • E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces
  • Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK
  • Table E1.30 J3 & J5 Interface Pinout
  • E1.4 J1 Front-Panel VGA/TMDS Interface
  • Figure E1.40 Standard Front-Panel VGA/TMDS Interface
  • Table E1.40 J1 Standard Front-Panel VGA/TMDS Pinout
  • Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D
  • Table E1.42 J2 DIP Switch Settings - TFT (24Bit TTL/CMOS)
  • E1.5 Rear I/O VGA Interface