Intel ESM-2743 - Manual (Page 35)

User’s Manual
ESM-2740/2743 User’s Manual 35
Signal Signal Description
REFSH#
REFSH# is pulled low whenever a refresh cycle is initiated. A refresh cycle is
activated every 15.6 us in order to prevent loss of DRAM data.
NOWS#
The Zero wait state signal tells the CPU to complete the current bus cycle without
inserting the default wait states. By default the CPU inserts 4 wait states for 8-bit
transfers and 1 wait state for 16-bit transfers.
MASTER#
This signal is used with a DRQ line to gain control of the system bus. A processor
or a DMA controller on the I/O channel may issue a DRQ to a DMA channel in
cascade mode and receive a DACK#. Upon receiving the DACK#, a bus master
may pull MASTER# low, which will allow it to control the system address, data and
control lines. After MASTER# is low, the bus master must wait one system clock
period before driving the address and data lines, and two clock periods before
issuing a read or write command. If this signal is held low for more than 15 us,
system memory may be lost as memory refresh is disabled during this process.
SYSCLK
SYSCLK is supplied by the CPU module and has a nominal frequency of about 8
MHz with a duty cycle of 40-60 percent. The frequency supplied by different CPU
modules may vary. This signal is supplied at all times except when the CPU
module is in sleep mode.
OSC
OSC is supplied by the CPU module. It has a nominal frequency of 14.31818 MHz
and a duty cycle of 40-60 percent. This signal is supplied at all times except when
the CPU module is in sleep mode.
RESETDRV
This active-high output is system reset generated from CPU modules. It is
responsible for resetting external devices.
DREQ
[0, 1, 2, 3, 5, 6, 7]
The asynchronous DMA request inputs are used by external devices to indicate
when they need service from the CPU modules DAM controllers. DREQ0..3 are
used for transfers between 8-bit I/O adapters and system memory. DREQ5..7 are
used for transfers between 16-bit I/O adapters and system memory. DRQ4 is not
available externally. All DRQ pins have pull-up resistors on the CPU modules.
DACK
[0, 1, 2, 3, 5, 6, 7]# DMA acknowledge 0..3 and 5.7 are used to acknowledge DMA requests. They are
active-low.
TC
The active-high output TC indicates that one of the DMA channels has transferred
all data.
IRQ [3:7, 9,15]
These are the asynchronous interrupt request lines. IRQ0, 1, 2 and 8 are not
available as external interrupts because they are used internally on the CPU
module. All IRQ signals are active-high. The interrupt requests are prioritized.
IRQ9 through IRQ12 and IRQ14 through IRQ15 have the highest priority (IRQ9 is
the highest). IRQ3 through IRQ7 have the lowest priority (IRQ7 is the lowest). An
interrupt request is generated when an IRQ line is raised from low to high. The line
must be held high until the CPU acknowledges the interrupt request (interrupt
service routine).