IBM 600/1200 Series - Manual

Continuum 600/1200 Series (PA-7100) Service Announcement
(8/12/98)
Revision History
12/23/97 - Revision 2.
02/24/98 - Updated Section 4; Added Section 6.
03/31/98 - Updated Section 8.4.
05/07/98 - Added Model 615 to Section 4.1.
06/02/98 - Updated Section 4.1.
06/16/98 - Updated Section 1 and Section 3.1.
06/22/98 - Updated Section 3.3.
07/06/98 - Reformatted Document.
07/20/98 - Updated Section 3.3.
07/27/98 - Updated Sections 4.1 and 4.3.
08/07/98 - Updated Section 6.1.
08/12/98 - Updated Section 4.1.
1. Overview
The Continuum 600/1200 Series systems are the first Stratus RISC systems based on the Hewlett Packard PA-RISC
HP7100 microprocessor and a new system bus architecture. The Series 600 is an entry-level to mid-range system
designed around a 6-slot backplane in the Central Electronic Cabinet (CEC). The Series 1200 version is an
expandable high-end system featuring a 12-slot CEC backplane.
The CEC cabinet main chassis boards in the 600/1200 Series include the following:
CPU-Memory Board - The CPU-Memory board is available in two designs: uniprocessor (one logical/ two
physical CPUs) and twin processor (two logical/four physical CPUs). Both are available in 72 or 96 MHz
versions with 256 KB instruction cache (Icache) and 256 KB data cache (Dcache) or 1 MB Icache and 1 MB
Dcache. Memory sizes range from 128 MB to 512 MB using 128-MB (M702) memory modules, or 512 MB to
2 GB using 512-MB (M713) memory modules. For the most current information on available memory refer to
the
Continuum Memory Subsystem Technical Reference . The document is also available in PDF format.at
http://www.cac.stratus.com/CSDoc/home/continuum600.htm .