Intel 8xC251TB - Manual (Page 18)

8xC251Tx Hardware Description
12
4.0 EXTENDED DATA FLOAT TIMING
The Extended Data Float Timing feature seeks to provide a solution to users that may be using slower
memory devices. Essentially, this feature extends the TRHDZ1 AC timing specification to accommodate
slower memory devices which require a longer period of dead time between a data and address bus cycles.
This feature is controlled by a bit in the Configuration byte (UCONFIG1). Bit 3 of UCONFIG1 in the 8xC251Tx
is defined as EDF#. In the 8xC251Sx, Bit 3 is defined as WSB. The implications of this change are discussed
below. Refer to Chapter 4 of the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller
User’s Manual (272795) for details of the device configuration for the 8xC251Sx. The information in that
chapter is valid for the 8xC251Tx with the exception of the change noted in this section.
4.1 Summary of the Extended Data Float Timing Changes
EDF# is used to determine whether the Extended Data Float Timing is enabled. Table 12 shows the definition
of UCONFIG1 for the 8xC251Tx. Only bit 3 has been redefined.
Refer to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded Microcontroller User’s Manual
(272795) for the AC timings specifications.
Table 12. UCONFIG1 bit definitions for the 8xC251Tx
Bit Number
Bit
Mnemonic
Function
7:5 - Reserved for Internal or Future Use.
Set these bits when programming UCONFIG1
4 INTR Interrupt Mode:
If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the PC
and PSW1). If this bit is clear, interrupts push the 2 lower bytes of the PC
onto the stack.
3 EDF# Extended Data Float Timings:
When cleared, the extended data float timings are enabled. When set,
8xC251Sx compatible AC timings are enabled
2:1 WSB1:0# External Wait State B (Region 01:):
WSB1# WSB2#
0 0 Inserts 3 wait states for region 01:
0 1 Inserts 2 wait states for region 01:
1 0 Inserts 1 wait state for region 01:
1 1 Zero wait states for region 01:
0 EMAP EPROM Map:
For devices with 16 Kbytes of on-chip code memory, clear this bit to map the
upper half of the on-chip code memory to region 00: (data memory). Maps
FF:2000H-FF:3FFFH to 00:E000H-00:FFFFH. If this bit is set, mapping does
not occur and the addresses in the range 00:E000H-00:FFFFH access
external RAM.