Icom IC-F51 - Manual (Page 9)

4 - 3
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The AF signals from the D/A converter (IC6, pin 3) change
the reactance of varactor diode (D18) to modulate the oscil-
lated signal at the TX VCO circuit (Q13, D16, D17). The
modulated VCO signal is amplified at the buffer amplifiers
(Q10, Q12) and is then applied to the drive amplifier circuit
via the T/R switch (D14).
The CTCSS/DTCS signals (“CENC0”, “CENC1”, ”CENC2”
from the CPU (FRONT unit; IC401, pins 79–81) pass
through the low-pass filter (IC403, pins 1, 3), and are then
applied to the D/A converter via the “CDCS” line (IC6, pin 9).
The output signal from the D/A converter (IC6, pin 10) pass-
es through the low-pass filter (IC5, pins 1, 2). The
CTCSS/DTCS signals are mixed with “MOD” signal at the
low-pass filter (IC5), and are then applied to the D/A con-
verter again (IC6, pin 4).
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
The drive/power amplifier circuits amplify the VCO oscillat-
ing signal to an output power level.
The signal from the VCO circuit passes through the T/R
switch (D14), and is amplified at the pre-drive (Q9), drive
(Q8), power (Q7) amplifiers to obtain 5 W of RF power (at
7.2 V DC).
The amplified signal is passed through the power detector
(D1), antenna switching circuit (D2) and low-pass filter (L1,
L2, C1–C5), and is then applied to the antenna connector
(CHASSIS unit; J1).
The bias current of the pre-drive (Q9), drive (Q8) and power
(Q7) amplifiers are controlled by the APC circuit.
4-2-4 APC CIRCUIT (MAIN UNIT)
The APC circuit (IC2, D1) protects the drive and power
amplifiers from excessive current drive, and selects output
power of HIGH, LOW2 or LOW1.
The power detector circuit (D1) detects the transmit power
output level and converts it into DC voltage. The output volt-
age is at a minimum level when the antenna impedance is
matched at 50
Ω and is increased when it is mismatched.
The detected voltage is applied to the differential amplifier
(IC2, pin 3), and the “T2” signal from the D/A converter (IC6,
pin 14), controlled by the CPU (FRONT unit; IC401), is
applied to the other input for reference. When antenna
impedance is mismatched, the detected voltage exceeds
the power setting voltage. Then the output voltage of the dif-
ferential amplifier (IC2, pin 4) controls the input current of
the pre-drive (Q9), drive (Q8) and power (Q7) amplifiers to
reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX/RX VCO circuits (Q13, Q14,
D16, D17, D19, D20). The oscillated signal is amplified at
the buffer amplifiers (Q11, Q12) and then applied to the PLL
IC (IC4, pin 8) after being passed through the low-pass filter
(L32, C206–C208).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the refer-
ence frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
Q7
Power
amp.
IC2
APC
amp.
Q8
Driver
amp.
+
—
Q9
Pre
drive
VCC
to antenna
T2
TMUT
D25
RF signal
from PLL circuit
T5V
APC control circuit
Power detector
circuit (D1)
D1
L4 L3
• APC CIRCUIT