Silicon Laboratories C8051F347 - Manual (Page 38)

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
38 Rev. 1.3
Figure 4.8. QFN-32 Package Drawing
Table 4.6. QFN-32 Package Dimensions
Dimension Min Nom Max
A 0.80 0.9 1.00
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 5.00 BSC
D2 3.20 3.30 3.40
e 0.50 BSC
E 5.00 BSC
E2 3.20 3.30 3.40
L 0.30 0.40 0.50
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
variation VHHD except for custom features D2, E2, and L which are
toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.