SMC Networks Sharp ARM720T_LH79520 - Manual (Page 14)

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor
The size of the RAM can vary between 1KB and 16MB, dependent on the availability of embedded block RAM in the target
FPGA device used. Memory size is configured in the Internal Processor Memory region of the Configure (32-bit Processors)
dialog (see the section
Configuring the Processor ).
Covering the processor's address space between 0000_0000h and 00FF_FFFFh, it will contain the reset and interrupt vectors,
as well as any speed or latency-sensitive code or data.
External Memory
Memory devices defined in the FPGA design are mapped into banks 1-4 of the processor's External Static Memory. Providing
for 256MB (64MB per bank), it covers the address space between 4400_0000h and 53FF_FFFFh.
The physical LH79520 device's External Bus Interface (EBI) provides a 26-bit address bus. In order to work with the wrapper's
Wishbone External Memory interface, which has 32-bit addressing, this 24-bit address is converted to a 32-bit address internal
to the wrapper.
The first part of the conversion involves the use of the value on the PER_WEB bus to evaluate the last two bits of the external
memory address as follows:
When PER_WEB = 0000, EXTMEMLow2Bits = "00"
When PER_WEB = 1100, EXTMEMLow2Bits = "00"
When PER_WEB = 0011, EXTMEMLow2Bits = "10"
When PER_WEB = 1110, EXTMEMLow2Bits = "00"
When PER_WEB = 1101, EXTMEMLow2Bits = "01"
When PER_WEB = 1011, EXTMEMLow2Bits = "10"
When PER_WEB = 0111, EXTMEMLow2Bits = "11"
The full address sent out on the ME_ADR_O bus is then determined, dependent on the memory bank being addressed, as
follows:
PER_CS(1) = 0 : ME_ADR_O = "010001" & PER_ADDR(25..2) & EXTMEMLow2Bits
PER_CS(2) = 0 : ME_ADR_O = "010010" & PER_ADDR(25..2) & EXTMEMLow2Bits
PER_CS(3) = 0 : ME_ADR_O = "010011" & PER_ADDR(25..2) & EXTMEMLow2Bits
PER_CS(4) = 0 : ME_ADR_O = "010100" & PER_ADDR(25..2) & EXTMEMLow2Bits
PER_CS(5) = 0 : ME_ADR_O = "00" & PER_ADDR(23..2) & EXTMEMLow2Bits
External Memory Interface Time-out
A simple time-out mechanism for the interface handles the case when attempting to access an address that does not exist, or if
the addressed target slave device is not operating correctly. This mechanism ensures that the processor will not be ‘locked’
indefinitely, waiting for an acknowledgement on its ME_ACK_I input.
After the ME_STB_O output is taken High a timer built-in to Altium Designer's ARM720T_LH79520 wrapper is started and the
physical ARM720T processor, which normally times out after 16 cycles, is requested to wait. If, after 4096 cycles of the external
clock signal (CLK_I), an acknowledge signal fails to appear from the addressed slave memory device, the wait request to the
ARM720T is dropped, the processor times out normally and the current data transfer cycle is forcibly terminated.
The ACK_O signal from a slave device should not be used as a ‘long delay’ hand-shaking mechanism. Where such a
mechanism needs to be implemented, either use polling or interrupts.
Peripheral I/O
The processor's Wishbone Peripheral I/O Interface is a one-way Wishbone Master, handling I/O in a very similar way to external
memory. The port can be used to communicate with any Wishbone Slave peripheral device.
Devices are mapped into bank 5 of the processor's External Static Memory and covers the address space between 5400_0000h
and 54FF_FFFFh. This address space of 16MB allows a physical address bus size of 24 bits.
Peripheral I/O Interface Time-out
A simple time-out mechanism for the interface handles the case when attempting to access an address that does not exist, or if
the addressed target slave device is not operating correctly. This mechanism ensures that the processor will not be ‘locked’
indefinitely, waiting for an acknowledgement on its IO_ACK_I input.
After the IO_STB_O output is taken High a timer built-in to Altium Designer's ARM720T_LH79520 wrapper is started and the
physical ARM720T processor, which normally times out after 16 cycles, is requested to wait. If, after 4096 cycles of the external
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