SMC Networks ARM PL241 User Manual
Primecell
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Table of contents
Document Outline
- PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual
- Contents
- List of Tables
- List of Figures
- Preface
- Introduction
- Functional Overview
- 2.1 Functional description
- 2.2 SMC
- 2.3 Functional operation
- 2.4 SMC functional operation
- Programmer’s Model
- 3.1 About the programmer’s model
- 3.2 Register summary
- 3.3 Register descriptions
- 3.3.1 SMC Memory Controller Status Register at 0x1000
- 3.3.2 SMC Memory Interface Configuration Register at 0x1004
- 3.3.3 SMC Set Configuration Register at 0x1008
- 3.3.4 SMC Clear Configuration Register at 0x100C
- 3.3.5 SMC Direct Command Register at 0x1010
- 3.3.6 SMC Set Cycles Register at 0x1014
- 3.3.7 SMC Set Opmode Register at 0x1018
- 3.3.8 SMC Refresh Period 0 Register at 0x1020
- 3.3.9 SMC SRAM Cycles Registers <0-3> at 0x1100, 0x1120, 0x1140, 0x1160
- 3.3.10 SMC Opmode Registers <0-3> at 0x1104, 0x1124, 0x1144, 0x1164
- 3.3.11 SMC User Status Register at 0x1200
- 3.3.12 SMC User Configuration Register at 0x1204
- 3.3.13 SMC Peripheral Identification Registers <0-3> at 0x1FE0-0x1FEC
- 3.3.14 SMC PrimeCell Identification Registers <0-3> at 0x1FF0-0x1FFC
- Programmer’s Model for Test
- Device Driver Requirements
- Signal Descriptions
- Glossary