Document Outline

• PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual
• Contents
• List of Tables
• List of Figures
• Preface
  • About this manual
    • Product revision status
    • Intended audience
    • Using this manual
    • Conventions
      • Typographical
      • Timing diagrams
      • Signals
      • Numbering
    • Further reading
      • ARM publications
  • Feedback
    • Feedback on this product
    • Feedback on this manual
• Introduction
  • 1.1 About the AHB MC
    • 1.1.1 AHB interface
    • 1.1.2 AHB to APB bridge
    • 1.1.3 SMC
    • 1.1.4 Clock domains
    • 1.1.5 Low-power interfaces
  • 1.2 Supported devices
• Functional Overview
  • 2.1 Functional description
    • 2.1.1 AHB interface
    • 2.1.2 AHB to APB bridge
    • 2.1.3 Clock domains
    • 2.1.4 Low-power interface
  • 2.2 SMC
    • 2.2.1 SMC interface
    • 2.2.2 APB slave interface
    • 2.2.3 Format
    • 2.2.4 Memory manager
    • 2.2.5 Memory interface
    • 2.2.6 Pad interface
    • 2.2.7 Interrupts
  • 2.3 Functional operation
    • 2.3.1 AHB interface operation
      • AHB fixed burst types
      • Undefined length INCR bursts
      • Broken bursts
      • Bufferable bit of the HPROT signal
      • Read after write hazard detection buffer
      • AHB response signals
      • Locked transfers
      • Registered HWDATA
      • Big-endian 32-bit mode
      • Removal of AHB error response logic
    • 2.3.2 AHB to APB bridge operation
    • 2.3.3 Clock domain operation
      • Static memory clocking options
    • 2.3.4 Low-power interface operation
  • 2.4 SMC functional operation
    • 2.4.1 Operating states
    • 2.4.2 Clocking and resets
      • Clocking
      • Resets
    • 2.4.3 Miscellaneous signals
    • 2.4.4 APB slave interface operation
    • 2.4.5 Format block
      • Hazard handling
      • SRAM memory accesses
    • 2.4.6 Memory manager operation
      • Low-power operation
      • Chip configuration registers
      • Direct commands
    • 2.4.7 Interrupts operation
    • 2.4.8 Memory interface operation
      • SRAM timing tables and diagrams
• Programmer’s Model
  • 3.1 About the programmer’s model
  • 3.2 Register summary
  • 3.3 Register descriptions
    • 3.3.1 SMC Memory Controller Status Register at 0x1000
    • 3.3.2 SMC Memory Interface Configuration Register at 0x1004
    • 3.3.3 SMC Set Configuration Register at 0x1008
    • 3.3.4 SMC Clear Configuration Register at 0x100C
    • 3.3.5 SMC Direct Command Register at 0x1010
    • 3.3.6 SMC Set Cycles Register at 0x1014
    • 3.3.7 SMC Set Opmode Register at 0x1018
    • 3.3.8 SMC Refresh Period 0 Register at 0x1020
    • 3.3.9 SMC SRAM Cycles Registers <0-3> at 0x1100, 0x1120, 0x1140, 0x1160
    • 3.3.10 SMC Opmode Registers <0-3> at 0x1104, 0x1124, 0x1144, 0x1164
    • 3.3.11 SMC User Status Register at 0x1200
    • 3.3.12 SMC User Configuration Register at 0x1204
    • 3.3.13 SMC Peripheral Identification Registers <0-3> at 0x1FE0-0x1FEC
      • SMC Peripheral Identification Register 0
      • SMC Peripheral Identification Register 1
      • SMC Peripheral Identification Register 2
      • SMC Peripheral Identification Register 3
    • 3.3.14 SMC PrimeCell Identification Registers <0-3> at 0x1FF0-0x1FFC
      • SMC PrimeCell Identification Register 0
      • SMC PrimeCell Identification Register 1
      • SMC PrimeCell Identification Register 2
      • SMC PrimeCell Identification Register 3
• Programmer’s Model for Test
  • 4.1 SMC integration test registers
    • 4.1.1 SMC Integration Configuration Register at 0x1E00
    • 4.1.2 Integration Inputs Register at 0x1E04
    • 4.1.3 Integration Outputs Register at 0x1E08
• Device Driver Requirements
  • 5.1 Memory initialization
• Signal Descriptions
  • A.1 About the signals list
  • A.2 Clocks and resets
  • A.3 AHB signals
  • A.4 SMC memory interface signals
  • A.5 SMC miscellaneous signals
  • A.6 Low-power interface
  • A.7 Configuration signal
  • A.8 Scan chains
• Glossary