Sony TAM-100 - Manual (Page 6)

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• IC Block Diagrams
U1 TC88512AF-043
U80 NJM2113M-TE2 U2 TC58A04F
5
6
7
8
2
3
4
1 BIAS
125k 50k
50k
4k
4k
#B
#A
V02
GND
V+
V01
CHIP–DIS
V REF
+VIN
–VIN
4M BIT
MEMORY
CELL ARRAY
CHARGE PUMP/
CONTROL GATE
DRIVE
INTERFACE/
CONTROL LOGIC
DATA LATCH
1 2 3 4 5 6 7
28
DECODER
VSS NC NC CS SK DI DO NC
VCC
8 – 14
NC
27 – 15
RIN
INT
12
9
10
11
13
3
4
14
15
16
17
18
19
20
21
81 82 83 84 85 86 90 91 92 93 94 76 77 78 79 80
1
2
.
64
63
.
44
43
.
5
8
33 36 22 24 29 32 25 28
ADDRESS DECODER
CLOCK
GENERATOR
+
PLL
MEMORY
INTERFACE
37, 38 39 40 41 42
61
62
65
66
67
68
69
70
71
72
73
74 75
48
45
56
49
60
57
I/O
CONTROL
8 BIT
CPU
1 1
89 87 100 95
A-D
CONVERTER
VRFF
GENERATOR
D-A
CONVERTER
DPS
• VOICE COMPRESSION/DECOMPRESSION
• DTMF DETECTION
• FULL DUPLEX HANDS FREE AND SO ON
1
HOST
SERIAL
INTERFACE
MEMORY
SERIAL
INTERFACE
CLOCK COUNTER
CPU PROGRAM
ROM
CPU RAM
DSP
INTERFACE
D7-D0 STBY RST MODE0-3 MODE0-3 A VDD1, 2 A VSS1, 2
TI+ SPO1- SPO2+ SPO2- DAO SPI1 SPO1+ VREF TI- TO ADI DVSS1-4 DVDD1-4
PA (3:0)
PD (3:0)
PE (1:0)
PB (7:0)
DVSS1-4
DVDD1-4
PA (7:4)
IORQ/PH3
MREQ/PH2
NM1
RD/PH1
WR/PH0
WAIT
AVDD1, 2
AVSS1, 2
A3-0/PM(3:0) A11-8/PJ(3:0) A7-4/PK(3:0)
ROUT
DVSS1-4 DVDD1-4 P A (7:4)
A 15-12/PI(3:0)
PC (3:0)
PVSS
MCE
OE/PF1
WE/PF0
RAS/PF3
CAS1/PF2
DVSS1-4
DVDD1-4
A 16
XIN
XOUT
PLLI
PVDD
PLLO
A15-12/PI(3:0)