Panasonic PanaXSeries MN103S65G - Manual (Page 8)

2-4 A 8-bit 16-bit timer, a peripheral initial
110: Timer 1 underflow
111: TMIN0 terminal input
TM1MD: Timer 1 mode register
Bit7 : Count operation permission
0: A stop of operation
1: Permission of operation
Bit6 : Base register setup
0: Usually, operation
1: Initialization
The value of a base register is loaded to a binary counter.
The timer pulse output 1 is reset on a low level.
Prohibition (0 fixation)
Bit 2-0: Clock source selection
000:IOCLK
001:IOCLK/8
010:IOCLK/32
011: Cascade connection with a timer 0
100: Timer 0 underflow
101: Prohibition of a setup
110: Timer 2 underflow
111: TMIN1 terminal input
TM2MD: Timer 2 mode register
Bit7 : Timer operation permission
0: A stop of operation
1: Permission of operation
Bit6 : Timer initialization
0: Usually, operation
1: Initialization
The value of a base register is loaded to a binary counter.
The timer pulse output 2 is reset on a low level.
Bit 5-3: Prohibition (0 fixation)
Bit2-0: Clock source selection
000:IOCLK
001:IOCLK/8
010:IOCLK/32
011: Cascade connection with a timer 1
100: Timer 0 underflow
2-31