National ADC12V170 - Manual (Page 4)

ADC12V170 Evaluation Board User’s Guide
N
- 4 - www.national.com
Rev 0.0
3.2 Connecting Power and Signal Sources
1. To power the ADC12V170 evaluation board,
connect a 5.0V power supply capable of supplying
up to 500mA to the green power connector labeled
“+5V” which is located along the bottom edge of
the ADC12V170 evaluation board.
2. Use the FutureBus connector (FB) to connect the
ADC12V170 evaluation board to the instrument
being used to capture the data from the evaluation
board. If the WaveVision Digital Interface Board is
being used for data capture, please consult the
WaveVision User’s Guide for details on installing
and operating the WaveVision hardware and
software system.
3. Connect the clock and signal inputs to the
CLK_IN_SE and AIN_XX (where XX = HF or LF)
SMA connectors.
4.0 Functional Description
4.1 Clock Input
The clock used to sample the analog input should be
applied to the CLK_IN_SE SMA connector (if using the
single-ended clock mode).
To achieve the best noise performance (best SNR), a
low jitter clock source with total additive jitter less than
150 fs should be used. A low jitter crystal oscillator is
recommended, but a sinusoidal signal generator with
low phase noise, such as the SMA100A from Rohde &
Schwarz or the HP8644B (discontinued) from Agilent /
Hewlett Packard, can also be used with a slight
degradation in the noise performance. When using a
low phase noise clock source, the SNR is primarily
degraded by the broadband noise of the signal
generator. The clock signal generator amplitude is
typically set to +19.9 dBm to produce the highest
possible slew rate, but the SNR performance will be
impacted minimally by lowering the signal generator
amplitude slightly. Placing a bandpass filter between
the clock source and the CLK_IN_SE SMA connector
will further improve the noise performance of the ADC
by filtering out the broadband noise of the clock source.
All results in the ADC12V170 datasheet are obtained
with a tunable bandpass filter made by Trilithic, Inc. in
the clock signal path.
The noise performance of the ADC12V170 can be
improved further by making the edge transitions of the
clock signal entering the ADC clock input (pin 11,
CLK+) very sharp. The ADC12V170 evaluation board
is assembled with a high speed buffer gate
(NC7WV125K8X, schematic reference designator U2)
in the clock input path to provide a sharp clock edge to
the clock inputs and improve the noise performance of
the ADC. The amplitude of the clock signal from the
NC7WV125K8X high speed buffer is 3.3V.
4.2 Analog Input
To obtain the best distortion results (best SFDR), the
analog input network on the evaluation board must be
optimized for the signal frequency being applied.
For analog input frequencies up to 150 MHz, the circuit
in Figure 2 is recommended. This is the configuration
of the assembled ADC12V170LFEB as it is delivered
from the factory. For input frequencies above 150
MHz, the circuit in Figure 3 is recommended. This is
the configuration of the assembled ADC12V170HFEB
as it is delivered from the factory.
A low noise signal generator such as the HP8644B is
recommended to drive the signal input of the
ADC12V170 evaluation board. The output of the signal
generator must be filtered to suppress the harmonic
distortion produced by the signal generator and to allow
accurate measurement of the ADC12V170 distortion
performance. A low pass or a bandpass filter is
recommended to filter the analog input signal. In some
cases, a second low pass filter may be necessary. The
bandpass filter on the analog input will further improve
the noise performance of the ADC by filtering the
broadband noise of the signal generator. Data shown
in the ADC12V170 datasheet was taken with a tunable
bandpass filter made by Trilithic in the analog signal
path.