Renesas H8S/2111B - Manual (Page 463)

Rev. 1.00, 05/04, page 429 of 544
Section 17 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register
(SYSCR).
Product Classification RAM Capacitance RAM Address
Flash memory version H8S/2111B-B 2 Kbytes H'E880 to H'EFFF,
H'FF00 to H'FF7F
H8S/2111B-C 3 Kbytes H'E480 to H'EFFF,
H'FF00 to H'FF7F