Renesas H8SX/1648 - Manual (Page 25)

9.2. Application Headers
Table 9-5 to Table 9-9 below show the standard application header connections.
JA1
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Generic Header Name CPU board
Signal Name
Device
Pin
1 5V CON_5V - 2 0V GROUND -
3 3V3 CON_3V3 - 4 0V GROUND -
5 AVCC CON_AVCC 121 6 AVss AVSS 123
7 AVref CON_VREF 125 8 ADTRG ADTRGn 87
9 AD0 AN0 118 10 AD1 AN1 119
11 AD2 AN2 120 12 AD3 AN3 122
13 DAC0 DA0 127 14 DAC1 DA1 128
15 IO_0 IO_0 144 16 IO_1 IO_1 1
17 IO_2 IO_2 2 18 IO_3 IO_3 3
19 IO_4 IO_4 42 20 IO_5 IO_5 43
21 IO_6 IO_6 44 22 IO_7 IO_7 5
23 IRQ3 IRQ3n 87 24 IIC_EX NC -
25 IIC_SDA SDA 8 26 IIC_SCL IIC_SCL 9
Table 9-5: JA1 Standard Generic Header
JA2
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Generic Header Name CPU board
Signal Name
Device
Pin
1 RESn RESn 91 2 EXTAL CON_EXTAL 98
3 NMIn NMI 61 4 VSS1 GROUND -
5 WDT_OVF WDT_OVFn 95 6 SCIaTX TXD1 59
7 IRQ0 IRQ0n 84 8 SCIaRX RXD1 55
9 IRQ1 IRQ1n 85 10 SCIaCK SCK1 54
11 UD UD 134 12 CTSRTS NC -
13 Up Up 56 14 Un Un 57
15 Vp Vp 63 16 Vn Vn 104
17 Wp Wp 105 18 Wn Wn 106
19 TMR0 TMR0 52 20 TMR1 TMR1 60
21 TRIGa TRIGa 49 22 TRIGb TRIGb 51
23 IRQ2 IRQ2n 86 24 TRISTn TRISTn 136
25 - - 26 - - -
Table 9-6: JA2 Standard Generic Header
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