Renesas HD151TS207SS - Manual (Page 6)

HD151TS207SS
Rev.1.00, Apr.25.2003, page 6 of 38
Block Diagram
3V66[3:1]
1/M2
SSC2
1/N2
1/M1
SSC1
1/N1
1/M0
1/N0
OSC
CK2
CK1
CK0
XTAL
14.318 MHz
REF[1:0]
(14.318MHz)
CPU[2:0]
CPU[2:0]#
* : Latched Input pin.
3.3 V VDD_48 3.3 V VDD_A VSS_48 VSS_A 6 × 3.3V VDD 6 × VSS VSS_IREF IREF
PCI[6:0]
SRC#
SRC
*SEL48_24
*FS_4/3/2A/B
*SEL33_25
*MODE
TEST_CLK#
*SEL66_48
*SEL100_200
VTT_PWRGD#
PWRDWN#/SAFE_F#
PCI_STOP#
SCLK
SDATA
Input
Clock
Select
PLL2
For
CPU
USB
PLL
PLL1
For
SRC
3V66
PCI
PCIF[2:0]
3V66_0/RESET#
3V66_4/VCH
USB_48
DOT_48
Control Logic
VCO0
VCO1
VCO2
Clock
Divider
Clock
Select
Delay
Control
Stop
Control