Toshiba MK4006GAH User Manual

Page 130

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Toshiba Corporation Digital Media Network Company

Page 130 of 153

© 2003, Copyright TOSHIBA Corporation All Rights Reserved

11.8.45.3.1.3 Word 2: Ultra DMA modes supported


Word 3 bits 5-0 contain the same information as contained in word 88 of the IDENTIFY DEVICE or IDENTIFY
PACKET DEVICE command response. Bits 15-6 of word 3 are reserved.

11.8.45.3.1.4 Words 3-6: Maximum LBA address


Words 4 through 7 define the maximum LBA address. This is the highest address accepted by the device in the
factory default condition. If no DEVICE CONFIGURATION SET command has been executed modifying the
factory default condition, this is the same value as that returned by a READ NATIVE MAX ADDRESS or READ
NATIVE MAX ADDRESS EXT command.

11.8.45.3.1.5 Word 7: Command/features set supported


Word 7 bit 0 if set to one indicates that the device is capable of supporting the SMART feature set.

Word 7 bit 1 if set to one indicates that the device is capable of supporting SMART self-test including the
self-test log.

Word 7 bit 2 if set to one indicates that the device is capable of supporting SMART error logging.

Word 7 bit 3 if set to one indicates that the device is capable of supporting the Security feature set.

Word 7 bit 4 if set to one indicates that the device is capable of supporting the Power-up in Standby feature set.

Word 7 bit 5 if set to one indicates that the device is capable of supporting the READ DMA QUEUED and
WRITE DMA QUEUED commands.

Word 7 bit 6 if set to one indicates that the device is capable of supporting the Automatic Acoustic Management
feature set.

Word 7 bit 7 if set to one indicates that the device is capable of supporting the Host Protected Area feature set.

Word 7 bit 8 if set to one indicates that the device is capable of supporting the 48-bit Addressing feature set.

Word 7 bits 9 through 15 are reserved.

11.8.45.3.1.6 Words 8-254: Reserved

11.8.45.3.1.7 Word 255: Integrity word


Bits 7:0 of this word shall contain the value A5h. Bits 15:8 of this word shall contain the data structure checksum.
The data structure checksum shall be the two’s complement of the sum of all byte in words 0 through 254 and
the byte consisting of bits 7:0 of word 255. Each byte shall be added with unsigned arithmetic, and overflow shall
be ignored. The sum of all bytes is zero when the checksum is correct.

11.8.45.4 Device Configuration Set

COMMAND CODE

1 0 1 1 0 0 0 1

REGISTER

REGISTER SETTING

NORMAL COMPLETION

DR

DRIVE No.

no change

CY na

no

change

HD na

no

change

SN na

no

change

SC na

no

change

FT C3h

no

change

LBA na

no

change

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