Vizio P42HDTV10A - Manual (Page 46)

CONFIDENTIAL – DO NOT COPY Page 8-14
File No. SG-0184
4. Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at
the rising edge of the clock (CLK). The DDR SDRAM has four independent banks; so two
Bank Select addresses (BA0, BA1) are required. The Bank Activation command to the first
read or write command must meet or exceed the minimum of RAS to CAS delay time (tRCD
min). Once a bank has been activated, it must be precharged before another Bank Activation
command can be applied to the same bank. The minimum time interval between interleaved
Bank Activation command (Bank A to Bank B and vice versa) is the Bank-to-Bank delay time
(tRRD min).
5. Read Bank
This command is used after the row activates command to initiate the burst read of data. The
read command is initiated by activating CS, CAS , and deasserting WE at the same clock
sampling (rising) edge as described in the command truth table. The length of the burst and
the CAS latency time will be determined by the values programmed during the MRS
command.
6. Write Bank
This command is used after the row activates command to initiate the burst write of data. The
write command is initiated by activating CS, CAS, and WE at the same clock sampling (rising)
edge as describe in the command truth table. The length of the burst will be determined by the
values programmed during the MRS command.