Xilinx LogiCORE IP CAN 3.2 - Manual (Page 23)

CAN Getting Started Guide www.xilinx.com 23
UG186 April 19, 2010
Implementation Scripts
Implementation Scripts
Note: Present only with a Full license.
The implementation script is either a shell script(.sh) or batch file (.bat) that processes the
example design through the Xilinx tool flow. It is located at:
Linux
<project_dir>/<component_name>/implement/implement.sh
Windows
<project_dir>/<component_name>/implement/implement.bat
When the CORE Generator software is run with the Full System Hardware Evaluation, or
Full license types, the implement script performs the following steps:
•
Synthesizes the HDL example design files using XST
•
Runs NGDBuild to consolidate the core netlist and the example design netlist into the
NGD file containing the entire design
• Maps the design to the target technology
• Place-and-routes the design on the target device
• Performs static timing analysis on the routed design using Timing Analyzer (TRCE)
• Generates a bitstream
• Enables Netgen to run on the routed design to generate a VHDL or Verilog netlist (as
appropriate for the Design Entry project setting) and timing information in the form
of SDF files
The Xilinx tool flow generates several output and report files. These are saved in the
following directory which is created by the implement script:
<project_dir>/<component_name>/implement/results
Simulation Scripts
Functional Simulation
The test scripts are ModelSim macros that automate the simulation of the test bench. They
are available from the following location:
<project_dir>/<component_name>/simulation/functional/
The test script performs the following tasks:
• Compiles the structural UniSim simulation model
• Compiles HDL Example Design source code
• Compiles the demonstration test bench
• Starts a simulation of the test bench
• Opens a Wave window and adds signals of interest (wave_mti.do/wave_ncsim.sv)
• Runs the simulation to completion