Absolute maximum ratings, t, Module – C&H Technology CM600DXL-24S User Manual

Page 3

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CM600DXL-24S
Dual IGBTMOD™ NX-S Series Module
600 Amperes/1200 Volts

Powerex, Inc., 173 Pavilion Lane, Youngwood, Pennsylvania 15697 (724) 925-7272 www.pwrx.com

2

06/11 Rev. 3

Absolute Maximum Ratings,

T

j

= 25°C unless otherwise specified

Inverter Part IGBT/FWDi

Characteristics

Symbol Rating Units

Collector-Emitter Voltage (V

GE

= 0V)

V

CES

1200 Volts

Gate-Emitter Voltage (V

CE

= 0V)

V

GES

±20 Volts

Collector Current (DC, T

C

= 119°C)

*2,*4

I

C

600 Amperes

Collector Current (Pulse, Repetitive)

*3

I

CRM

1200 Amperes

Total Power Dissipation (T

C

= 25°C)

*2,*4

P

tot

4545 Watts

Emitter Current (T

C

= 25°C)

*2,*4

I

E

*1

600 Amperes

Emitter Current (Pulse, Repetitive)

*3

I

ERM

*1

1200 Amperes

Module

Characteristics

Symbol Rating Units

Maximum Junction Temperature

T

j(max)

175 °C

Maximum Case Temperature

*2

T

C(max)

125 °C

Operating Junction Temperature

T

j(op)

-40 to +150

°C

Storage Temperature

T

stg

-40 to +125

°C

Isolation Voltage (Terminals to Baseplate, f = 60Hz, AC 1 minute)

V

ISO

2500 Volts

*1 Represent ratings and characteristics of the anti-parallel, emitter-to-collector free wheeling

diode (FWDi).

*2 Case temperature (T

C

) and heatsink temperature (T

s

) is measured on the surface

(mounting side) of the baseplate and the heatsink side just under the chips.

Refer to the figure to the right for chip location.

The heatsink thermal resistance should be measured just under the chips.

*3 Pulse width and repetition rate should be such that device junction temperature (T

j

)

does not exceed T

j(max)

rating.

*4 Junction temperature (T

j

) should not increase beyond maximum junction

temperature (T

j(max)

) rating.

0

20.9

32.6

46.0

72.6

86.0

0

26.4

40.0

72.2

85.8

0

27.2

57.6

81.8

98.6

93.9

53.2

22.9

0

LABEL SIDE

Tr1 / Tr2: IGBT, Di1 / Di2: FWDi, Th: NTC Thermistor

Each mark points to the center position of each chip.

Di2

Th

Tr2

Di2

Tr2

Di2

Tr2

Di1

Tr1

Di1

Tr1

Di1

Tr1

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