Pin description (continued) – Rainbow Electronics MAX98089 User Manual
Page 58
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MAX98089
Low-Power, Stereo Audio Codec
with FlexSound Technology
Pin Description (continued)
BUMP
(WLP)
PIN
(TQFN-EP)
NAME
FUNCTION
E1
6
DVDDS1
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF ca-
pacitor.
E2
5
MCLK
Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
E4
9
SDINS1
S1 Digital Audio Serial-Data DAC Input. The input/output voltage is referenced to
DVDDS1.
E5
56
IRQ
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in
status register 0x00 change state. Read status register 0x00 to clear IRQ once
set. Repeat faults have no effect on IRQ until it is cleared by reading the I
2
C status
register 0x00. Connect a 10kI pullup resistor to DVDD for full output swing.
E6
45
JACKSNS
Jack Sense. Detects the insertion and removal of a jack. In typical applications,
connect JACKSNS to the MIC pole of the jack. See the Jack Detection section.
E7
37
INB1
Single-Ended Line Input B1. Also negative differential line input B.
E8
40
MIC1P/
DIGMICDATA
Positive Differential Microphone 1 Input. AC-couple a microphone with a series
1FF capacitor. Can be retasked as a digital microphone data input.
E9
38
INA2/
EXTMICN
Single-Ended Line Input A2. Also positive differential line input A or negative dif-
ferential external microphone input.
F1
3
DGND
Digital Ground
F2
2
BCLKS2
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave
mode and an output when in master mode. The input/output voltage is referenced
to DVDDS2.
F3
4
LRCLKS2
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate
clock and determines whether audio data on S2 is routed to the left or right chan-
nel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the
IC is in slave mode and an output when in master mode. The input/output voltage
is referenced to DVDDS2.
F4
52
SDA
I
2
C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output
swing.
F5
51
SCL
I
2
C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing.
F6
49
REG
Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
F7
44
MICBIAS
Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external 2.2kI resis-
tor should be placed between MICBIAS and the microphone output.
F8
41
MIC1N/
DIGMICCLK
Negative Differential Microphone 1 Input. AC-couple a microphone with a series
1FF capacitor. Can be retasked as a digital microphone clock output.
F9
39
INA1/
EXTMICP
Single-Ended Line Input A1. Also negative differential line input A or positive dif-
ferential external microphone input.