Rainbow Electronics MAX11042 - Manual (Page 9)

Reading the FIFO While the Key is Still Pressed
When a valid keypress occurs, INT goes low, signaling
to the processor that a key has been pressed (see
Figure 3). If the processor reads the FIFO while the key
is still pressed, the key type and current duration of the
keypress is sent. The current keypress information in
the FIFO is not cleared after a read operation if the key
is still pressed. In addition, after a read operation, if the
key is still pressed, INT goes high again until the device
detects another keypress/release, freeing the proces-
sor from polling. Conversely, if the processor chooses
to poll the duration of the keypress, INT stays high at
this time no matter how many times the processor
reads the FIFO. When INT goes low again (from anoth-
er keypress/release), key type and final time duration of
the keypress is available in the FIFO. When the FIFO is
read after the key release, the information from that
keypress is cleared and INT goes high again.
Reading the FIFO After the Key has Released
When a valid keypress occurs, INT goes low, signaling
to the processor that a key has been pressed (see
Figure 4). If the processor reads the FIFO after the key
has already been released (or an additional key was
pressed), the key type and final duration time of that
keypress is sent. In addition, the information from the
keypress is cleared and INT goes high again.
Digital Serial Interface
The MAX11041/MAX11042 contain an I 2 C-compatible
interface for data communication with a host processor
(SCL and SDA). The interface supports a clock fre-
quency up to 400kHz. SCL and SDA require pullup
resistors that are connected to a positive supply. Figure
5 details the read and write formats.
Write Format
The only write to the MAX11041/MAX11042 that is possi-
ble is to the control register (C7–C0). Use the following
sequence to write to the control register (see Figure 5):
1) After generating a start condition (S), address the
MAX11041/MAX11042 by sending the appropriate
slave address byte with its corresponding R/W bit
set to a 0 (see the Slave Address and R/W Bit sec-
tion). The MAX11041/MAX11042 answer with an
ACK bit (see the Acknowledge Bits section).
2) Send the appropriate data bytes to program the
control register (C7–C0). The MAX11041/MAX11042
answer with an ACK bit.
3) Generate a stop condition (P).
Read Format
To read the control register and key type/duration stored
in FIFO, use the following sequence (see Figure 5):
1) After generating a start condition (S), address the
MAX11041/MAX11042 by sending the appropriate
slave address byte with its corresponding R/W bit
set to a 1 (see the Slave Address and R/W Bit sec-
tion). The MAX11041/MAX11042 answer with an
ACK bit (see the Acknowledge Bits section).
2) The MAX11041/MAX11042 send the 8-bit chip ID
I7–I0. Afterwards, the master must send an ACK bit.
3) The MAX11041/MAX11042 send the contents of the
control register (C7–C0) starting with the most sig-
nificant bit. Afterwards, the master must send an
ACK bit.
MAX11041/MAX11042
Wired Remote Controllers
____________________________________________________________________________________ 9
START
ADDRESS
BYTE 0
ACK STOP
5 BITS 0
ACK
START
ADDRESS
BYTE 0 R/ W ACK STOP
1
CHIP ID
BYTE 1
I7–I0
ACK
CONTROL
REG DATA
BYTE 2
ACK
KEY TYPE
BYTE 3 ACK
KEY
DURATION
BYTE 4
ACK
S P A A A1 A0
5 BITS A1 A0 S A A A A A P
READ FORMAT
C7–C0 K7–K0 OF, T6–T0
R/ W
CONTROL
REG DATA
BYTE 1
C7–C0
WRITE FORMAT
SLAVE TO MASTER
MASTER TO SLAVE
Figure 5. Read/Write Formats