Rainbow Electronics MAX5183 User Manual
Page 12
MAX5180/MAX5183
Dual, 10-Bit, 40MHz, Current/Voltage
Simultaneous-Output DACs
12
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Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fun-
damental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5180. The differential
voltage across OUT1P (or OUT2P) and OUT1N (or
OUT2N) is converted into a single-ended voltage by
designing an appropriate operational amplifier configu-
ration (Figure 6).
I/Q Reconstruction in a QAM Application
The MAX5180/MAX5183’s low-distortion supports ana-
log reconstruction of in-phase (I) and quadrature (Q)
carrier components typically used in QAM (quadrature
amplitude modulation) architectures where I and Q
data are interleaved on a common data bus. A QAM
signal is a carrier frequency that is both amplitude and
phase modulated, and is created by summing two
independently modulated carriers of identical frequency
but different phase (90° phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain and the MAX5180/
MAX5183’s dual DACs may be used to reconstruct the
analog I and Q components.
The I/Q reconstruction system is completed by a quad-
rature modulator that combines the reconstructed I and
Q components with in-phase and quadrature phase
carrier frequencies, then sums both outputs to provide
the QAM signal.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influ-
ence the MAX5180/MAX5183’s performance. Unwanted
digital crosstalk may couple through the input, refer-
ence, power-supply, and ground connections, which
may affect dynamic specifications like signal-to-noise
ratio or spurious-free dynamic range. In addition, elec-
tromagnetic interference (EMI) can either couple into or
be generated by the MAX5180/MAX5183. Therefore,
grounding and power-supply decoupling guidelines for
high-speed, high-frequency applications should be
closely followed.
First, a multilayer pc board with separate ground and
power-supply planes is recommended. High-speed
signals should be run on controlled impedance lines
directly above the ground plane. Since the MAX5180/
MAX5183 have separate analog and digital ground
buses (AGND and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
Both devices have two power-supply inputs: analog
V
DD
(AV
DD
) and digital V
DD
(DV
DD
). Each AV
DD
input
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors. These capacitors should be as
close to the pin as possible, and their opposite ends
should be as close to the ground plane as possible. The
DV
DD
pins should also have separate 10µF and 0.1µF
capacitors adjacent to their respective pins. Try to mini-
mize analog load capacitance for proper operation. For
best performance, it is recommended to bypass CREF1
and CREF2 with low-ESR 0.1µF capacitors to AV
DD
.
THD
V
V
V
V
V
=
×
+
+
+
20
2
2
3
2
4
2
5
2
1
log