Rainbow Electronics MAX12553 - Manual (Page 16)

MAX12553
All three modes of reference operation require the
same bypass capacitor combinations. Bypass COM
with a 2.2µF capacitor to GND. Bypass REFP and
REFN each with a 0.1µF capacitor to GND. Bypass
REFP to REFN with a 1µF capacitor in parallel with a
10µF capacitor.
Place the 1µF capacitor as close to
the device as possible on the same side of the PC
board
. Bypass REFIN and REFOUT to GND with a
0.1µF capacitor.
For detailed circuit suggestions, see Figure 13 and
Figure 14.
Clock Input and Clock Control Lines
(CLKP, CLKN, CLKTYP)
The MAX12553 accepts both differential and single-
ended clock inputs. For single-ended clock input oper-
ation, connect CLKTYP to GND, CLKN to GND, and
drive CLKP with the external single-ended clock signal.
For differential clock input operation, connect CLKTYP
to OV
DD
or V
DD
, and drive CLKP and CLKN with the
external differential clock signal. To reduce clock jitter,
the external single-ended clock must have sharp falling
edges. Consider the clock input as an analog input and
route it away from any other analog inputs and digital
signal lines.
CLKP and CLKN are high impedance when the
MAX12553 is powered down (Figure 5).
Low clock jitter is required for the specified SNR perfor-
mance of the MAX12553. Analog input sampling
occurs on the falling edge of the clock signal, requiring
this edge to have the lowest possible jitter. Jitter limits
the maximum SNR performance of any ADC according
to the following relationship:
where f IN represents the analog input frequency and t J
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 71dB of SNR with an input frequen-
cy of 175MHz, the system must have less than 0.25ps
of clock jitter. In actuality, there are other noise sources
such as thermal noise and quantization noise that con-
tribute to the system noise, requiring the clock jitter to
be less than 0.2ps to obtain the specified 71dB of SNR
at 175MHz.
Clock Duty-Cycle Equalizer (DCE)
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12553 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Disabling the clock duty-cycle equalizer reduces the
analog supply current by 1.5mA.
SNR
f t
IN J
log = Ч
Ч π ×





 20
1
2
14-Bit, 65Msps, 3.3V ADC
16 ______________________________________________________________________________________
MAX12553
CLKP
CLKN
V DD
GND
10kΩ
10kΩ
10kΩ
10kΩ
DUTY-CYCLE
EQUALIZER
SWITCHES S
1_
AND S
2_
ARE OPEN
DURING POWER-DOWN, MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S
2_
ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
S 1H
S
2H
S
1L
S
2L
Figure 5. Simplified Clock-Input Circuit