Step immunity and no r, Sense – Rainbow Electronics MAX5937 User Manual
Page 9
MAX5936/MAX5937
-48V Hot-Swap Controllers with V
IN
Step Immunity and No R
SENSE
_______________________________________________________________________________________
9
In a normal power-up GATE cycle, the voltage at V
OUT
(referenced to V
EE
) ramps to below 74% of the circuit-
breaker threshold voltage, V
CB
. At this time, the remaining
GATE voltage is rapidly pulled up to full enhancement.
PGOOD is asserted 1.26ms after GATE is fully enhanced
(see Figure 4). If the voltage at V
OUT
remains above 74%
of the V
CB
(when GATE reaches 90% of full enhance-
ment), then a power-up to fault management fault has
occurred (see Figure 5). GATE is rapidly pulled to V
EE
,
turning off the power MOSFET and disconnecting the
load. PGOOD remains deasserted and the MAX5936/
MAX5937 enter the fault management mode.
When the power MOSFET is fully enhanced, the
MAX5936/MAX5937 monitor the drain voltage (V
OUT
) for
circuit-breaker and short-circuit faults. The MAX5936/
MAX5937 make use of the power MOSFET’s R
DS(ON)
as
the current-sense resistance to detect excessive current
through the load. The short-circuit threshold voltage,
V
SC
, is twice V
CB
(V
SC
= 2 x V
CB
) and is available in
100mV, 200mV, and 400mV thresholds. V
CB
and V
SC
are temperature-compensated (increasing with tempera-
ture) to track the normalized temperature coefficient of
R
DS(ON)
for typical power MOSFETs.
When the load current is increased during full enhance-
ment, this causes V
OUT
to exceed V
CB
but remains less
than V
SC
, and starts the 1.2ms circuit-breaker glitch
rejection timer. At the end of the glitch rejection period,
if V
OUT
still exceeds V
CB
, the GATE is immediately
pulled to V
EE
(330ns), PGOOD (PGOOD) is deasserted,
and the part enters fault management. Alternatively,
during full enhancement when V
OUT
exceeds V
SC
,
there is no glitch rejection timer. GATE is immediately
pulled to V
EE
, PGOOD is deasserted, and the part
enters fault management.
Figure 3. Load Probe Test During Initial Power-Up
40ms/div
V
EE
20V/div
V
LP
20V/div
V
OUT
20V/div
ALL VOLTAGES
REFERENCED TO GND
Figure 2. GATE Voltage Clamp During Power-Up
V
IN
20V/div
V
GATE
1V/div
4ms/div
C
IN
= 100µF
Figure 4. MAX5936 Normal Condition
V
IN
50V/div
V
PGOOD
50V/div
40ms/div
V
GATE
10V/div
V
OUT
50V/div
I
IN
2A/div
Figure 5. MAX5936 Startup in Fault Condition
V
IN
50V/div
V
PGOOD
50V/div
40ms/div
V
GATE
10V/div
V
OUT
50V/div
I
IN
2A/div