Rainbow Electronics MAX15020 - Manual (Page 13)

MAX15020
2A, 40V Step-Down DC-DC Converter with
Dynamic Output-Voltage Programming
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Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the
input capacitor must be carefully chosen to keep the
input-voltage ripple within design requirements. The
input-voltage ripple is comprised of
∆V
Q (caused by the
capacitor discharge) and
∆V
ESR (caused by the ESR
(equivalent series resistance) of the input capacitor).
The total voltage ripple is the sum of
∆V
Q and
∆V
ESR .
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
where:
I OUT_MAX is the maximum output current, D is the duty
cycle, and f SW is the switching frequency.
The MAX15020 includes internal and external UVLO
hysteresis and soft-start to avoid possible unintentional
chattering during turn-on. However, use a bulk capaci-
tor if the input source impedance is high. Use enough
input capacitance at lower input voltages to avoid pos-
sible undershoot below the UVLO threshold during
transient loading.
Output Capacitor Selection
The allowable output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the output capacitance and its ESR. The output
ripple is mainly composed of
∆V
Q
(caused by the
capacitor discharge) and ∆V
ESR
(caused by the volt-
age drop across the ESR of the output capacitor). The
equations for calculating the peak-to-peak output volt-
age ripple are:
Normally, a good approximation of the output-voltage
ripple is
∆V
RIPPLE ≈
∆V
ESR +
∆V
Q . If using ceramic
capacitors, assume the contribution to the output-volt-
age ripple from ESR and the capacitor discharge to be
equal to 20% and 80%, respectively.
∆I
L
is the peak-to-
peak inductor current (see the Input Capacitor
Selection section) and f SW is the converter’s switching
frequency.
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
greater duty cycle. The response time (t
RESPONSE )
depends on the closed-loop bandwidth of the converter
(see the
Compensation Design section). The resistive
drop across the output capacitor’s ESR, the drop
across the capacitor’s ESL (
∆V
ESL ), and the capacitor
discharge cause a voltage droop during the load step.
Use a combination of low-ESR tantalum/aluminum elec-
trolytic and ceramic capacitors for better transient load
and voltage ripple performance. Surface-mount capaci-
tors and capacitors in parallel help reduce the ESL.
Keep the maximum output-voltage deviations below the
tolerable limits of the electronics powered. Use the fol-
lowing equations to calculate the required ESR, ESL,
and capacitance value during a load step:
where I STEP is the load step, t STEP is the rise time of the
load step, and t RESPONSE is the response time of the
controller.
ESR
V
I
C
I t
V
ESL
V t
I
ESR
STEP
OUT
STEP RESPONSE
Q
ESL STEP
STEP
=
=
Ч
=
Ч
∆
∆
∆
∆
∆ ∆
V
I
C f
V ESR I
Q
L
OUT SW
ESR L
=
Ч Ч
= Ч
16
∆I
V V V
V f L
D
V
V
L
IN OUT OUT
IN SW
OUT
IN
=
Ч
Ч Ч
=
− ( )
ESR
V
I
I
C
I D D
V f
ESR
OUT MAX
L
IN
OUT MAX
Q SW
=
+
⎛
⎝⎜ ⎞
⎠⎟
=
Ч
Ч
−
∆
∆
∆
_
_
( )
2
1