Max9489 multiple-output network clock generator, Serial interface timing – Rainbow Electronics MAX9489 User Manual
Page 4
MAX9489
Multiple-Output Network Clock Generator
4
_______________________________________________________________________________________
Note 1: All DC parameters tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: No high output level is specified but only the output resistance to the bus. For I
2
C, the high-level voltage is provided by
pullup resistors on the bus.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Note 5: C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3(V
DD
) and 0.7(V
DD
).
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
SERIAL INTERFACE TIMING
(V
DD
= AV
DD
= +3.3V, T
A
= -40°C to +85°C.) (Note 1, Figure 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock
f
SCL
400
kHz
Bus Free Time Between STOP
and START Conditions
t
BUF
1.3
µs
Hold Time, Repeated START
Condition
t
HD,STA
0.6
µs
Repeated START Condition
Setup Time
t
SU,STA
0.6
µs
STOP Condition Setup Time
t
SU,STO
0.6
µs
Data Hold Time Master
t
HD,DAT
(Note 4)
15
900
ns
Data Hold Time Slave
t
HD,DAT
(Note 4)
15
900
ns
Data Setup Time
t
SU,DAT
100
ns
SCL Clock Low Period
t
LOW
1.3
µs
SCL Clock High Period
t
HIGH
0.7
µs
Rise Time of SDA and SCL,
Receiving
t
R
(Notes 2, 5)
20 +
0.1C
b
300
ns
Fall Time of SDA and SCL,
Receiving
t
F
(Notes 2, 5)
20 +
0.1C
b
300
ns
Fall Time of SDA, Transmitting
t
F,TX
(Notes 2, 5)
20 +
0.1C
b
250
ns
Pulse Width of Spike Suppressed
t
SP
(Notes 2, 6)
0
50
ns
Capacitive Load for Each Bus
Line
C
b
(Note 2)
400
pF