Rainbow Electronics MAX5974D - Manual (Page 19)

MAX5974A/MAX5974B/MAX5974C/MAX5974D
Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
19
Frequency Foldback for High-Efficiency
Light-Load Operation
The frequency foldback threshold can be programmed
from 0 to 20% of the full load current using a resistor from
FFB to GND.
When V
CSAVG falls below V FFB , the device folds back
the switching frequency to 1/2 the original value to
reduce switching losses and increase the converter effi-
ciency. Calculate the value of R
FFB as follows:
LOAD(LIGHT) CS
FFB
FFB
10 I R
R
I
Ч Ч
=
where R FFB is the resistor between FFB and GND,
I LOAD(LIGHT) is the current at light-load conditions that
triggers frequency foldback, R CS is the value of the
sense resistor connected between CS and PGND, and
I
FFB is the current sourced from FFB to R FFB (30FA typ).
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (V
SS ), and the
voltage (2.43V - V DCLMP ). The maximum duty cycle is
calculated as:
MIN
MAX
V
D
2.43V
=
where V MIN = minimum (2V, V SS , 2.43V - V DCLMP ).
SS
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. V
SS is
calculated as follows:
SS SS SS-CH
V R I = ×
where R SS is the resistor connected between SS and
GND, and I SS-CH is the current sourced from SS to R SS
(10FA typ).
DCLMP
To set D MAX using supply voltage feed-forward, connect
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Application Circuits.
This feed-forward duty-cycle clamp ensures that the
external n-channel MOSFET is not stressed during sup-
ply transients. V
DCLMP is calculated as follows:
DCLMP2
DCLMP S
DCLMP1 DCLMP2
R
V V
R R
= ×
+
where R DCLMP1 and R DCLMP2 are the resistive divider
values shown in the Typical Application Circuits and V
S
is the input supply voltage.
Oscillator Synchronization
The internal oscillator can be synchronized to an external
clock by applying the clock to DITHER/SYNC directly. The
external clock frequency can be set anywhere between
1.1x to 2x the internal clock frequency.
Using an external clock increases the maximum duty
cycle by a factor equal to f
SYNC
/f
SW
. This factor should
be accounted for in setting the maximum duty cycle
using any of the methods described in the Duty-Cycle
Clamping section. The formula below shows how the
maximum duty cycle is affected by the external clock
frequency:
SYNC MIN
MAX
SW
f V
D
2.43V f
= ×
where V MIN is described in the Duty-Cycle Clamping
section, f SW is the switching frequency as set by the
resistor connected between RT and GND, and f SYNC is
the external clock frequency.
Frequency Dithering for Spread-
Spectrum Applications (Low EMI)
The switching frequency of the converter can be dith-
ered in a range of Q10% by connecting a capacitor from
DITHER/SYNC to GND, and a resistor from DITHER to
RT as shown in the Typical Application Circuits. This
results in lower EMI.
A current source at DITHER/SYNC charges the capaci-
tor C
DITHER to 2V at 50FA. Upon reaching this trip point,
it discharges C DITHER to 0.4V at 50FA. The charging
and discharging of the capacitor generates a triangular
waveform on DITHER/SYNC with peak levels at 0.4V and
2V and a frequency that is equal to:
TRI
DITHER
50 A
f
C 3.2V
µ
=
Ч