Rainbow Electronics MAX5811 - Manual (Page 9)

MAX5811
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
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low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5811. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see
Acknowledge Bit). The STOP condition frees the bus. If
a repeated START condition (Sr) is generated instead of
a STOP condition, the bus remains active. When a
STOP condition or incorrect address is detected, the
MAX5811 internally disconnects SCL from the serial
interface until the next START condition, minimizing digi-
tal noise and feedthrough.
Early STOP Conditions
The MAX5811 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition (Figure 3).
This condition is not a legal I
2 C format; at least one
clock pulse must separate any START and STOP condi-
tions.
Repeated START Conditions
A REPEATED START (S r ) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S
r may also be used when the bus
master is writing to several I 2 C devices and does not
want to relinquish control of the bus. The MAX5811 ser-
ial interface supports continuous write operations with
or without an S
r condition separating them. Continuous
read operations require S r conditions because of the
change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5811 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5811 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address (Figure 4). When idle, the MAX5811
waits for a START condition followed by its slave
address. The serial interface compares each address
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or read-
ing from the MAX5811 (R/W = 0 selects the write condi-
tion, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5811 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5811 has eight different factory/user-pro-
grammed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
to V
DD sets A0 = 1. This feature allows up to eight
MAX5811s to share the same bus.
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5811 (Figure 5). Bits C3–C0 con-
figure the MAX5811 (Table 3). Bits D9–D0 are DAC
data. Bits S1 and S0 are sub-bits and are always zero.
Input and DAC registers update on the falling edge of
SCL during the acknowledge bit. Should the write cycle
be prematurely aborted, data is not updated and the
S A6 A5 A4 A3 A2 A1 A0 R/W
Figure 4. Slave Address Byte Definition
Table 2. MAX5811 I 2 C Slave Addresses
PART V ADD
DEVICE ADDRESS
(A 6 ...A 0 )
MAX5811L GND 0010 000
MAX5811L V DD 0010 001
MAX5811M GND 0010 010
MAX5811M V DD 0010 011
MAX5811N GND 0110 100
MAX5811N V DD 0110 101
MAX5811P GND 1010 100
MAX5811P V DD 1010 101
C3 C2 C1 C0 D9 D8 D7 D6
Figure 5. Command Byte Definition