Figure 20), Figure 20, Figure 21 – Rainbow Electronics T5761 User Manual
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T5760/T5761
4561B–RKE–10/02
Figure 20.
Timing Diagram of the Data Clock
Figure 21.
Data Clock Disappears Because of a Timing Error
Figure 22.
Data Clock Disappears Because of a Logical Error
Dem_out
Data_out (DATA)
DATA_CLK
'1'
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Bit check ok
Preburst
Data
t
Delay
t
P_Data_Clk
T
2T
Receiving mode,
data clock control logic active
Bit-check mode
Start bit
Dem_out
Data_out (DATA)
DATA_CLK
'1'
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Timing error
Data
(T
ee
< T
Lim_min
OR T
Lim_max
<T
ee
< T
Lim_min_2T
OR T
ee
> T
Lim_max_2T
)
T
ee
Receiving mode,
bit check active
Receiving mode,
data clock control
logic active
Dem_out
Data_out (DATA)
DATA_CLK
'1'
'1'
'1'
'0'
'1'
'1'
'?'
'0'
'0'
'1'
'0'
Logical error (Manchester code violation)
Data
Receiving mode,
bit check aktive
Receiving mode,
data clock control
logic active