Rainbow Electronics ATtiny28L - Manual (Page 38)

38
ATtiny28L/V
1062E–10/01
Port A Schematics Note that all port pins are synchronized. The synchronization latches are, however, not
shown in the figures.
Figure 29. Port A Schematic Diagram (Pins PA0, PA1 and PA3)
Figure 30. Port A Schematic Diagram (Pin PA2)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
PAn
WP:
WD:
RL:
RP:
RD:
n:
WRITE PORTA
WRITE DDRA
READ PORTA LATCH
READ PORTA PIN
READ DDRA
0,1,3
DDAn
PORTAn
RL
RP
MOS
PULL-
UP
D Q
RESET
R
C
R
R
DATA BUS
D Q
RESET
C
WP
WP:
RL:
WRITE PORTA
READ PORTA LATCH
PORTA2
RL
1
0
HARDWARE
MODULATOR
PA2
D Q
RESET
C
OOM01
0
0
1
1
OOM00
0
1
0
1
DISABLE
TOGGLE
CLEAR
SET
TOV0
FOV0
R
Note: Both the flip-flops shown
have reset value one (set).
R