Rainbow Electronics AT90S8515 - Manual (Page 8)

8
AT90S8515
0841G–09/01
Figure 4. The AT90S8515 AVR RISC Architecture
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the beginning of the program
memory. The different interrupts have priority in accordance with their interrupt vector
position. The lower the interrupt vector address, the higher the priority.
Data Bus 8-bit
4K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Test
32 x 8
General
Purpose
Registers
ALU
512 x 8
Data
SRAM
Direct Addressing
Indirect Addressing
Control
Registers
Interrupt
Unit
SPI
Unit
Serial
UART
8-bit
Timer/Counter
16-bit
Timer/Counter
with PWM
Watchdog
Timer
Analog
Comparator
32
I/O Lines
512 x 8
EEPROM