Rainbow Electronics ATV750BL - Manual (Page 9)

9
ATV750B(L)
0301I–08/01
Preload of
Registered
Outputs
The ATV750B(L) registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
IH
level on the I/O pin will force the reg-
ister high; a V
IL
will force it low, independent of the output polarity. The PRELOAD state is
entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When
the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the
Select Pin.
Level Forced on Registered
Output Pin during
PRELOAD Cycle
Select Pin
State
Register #0 State after
Cycle
Register #1 State after
Cycle
V
IH
Low High X
V
IL
Low Low X
V
IH
High X High
V
IL
High X Low