Rainbow Electronics DS1220AB_AD User Manual

Rainbow Electronics Storage

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E

Copyright 1995 by Dallas Semiconductor Corporation.

All Rights Reserved. For important information regarding

patents and other intellectual property rights, please refer to

Dallas Semiconductor data books.

DS1220AB/AD

16K Nonvolatile SRAM

DS1220AB/AD

100495 1/10

2

FEATURES

10 years minimum data retention in the absence of
external power

Data is automatically protected during power loss

Directly replaces 2K x 8 volatile static RAM or
EEPROM

Unlimited write cycles

Low-power CMOS

JEDEC standard 24–pin DIP package

Read and write access times as fast as 100 ns

Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time

Full +10% V

CC

operating range (DS1220AD)

Optional +5% V

CC

operating range (DS1220AB)

Optional industrial temperature range of -40

°

C to

+85

°

C, designated IND

PIN ASSIGNMENT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A8

A9

A10

DQ7

DQ6

DQ5

DQ4

DQ3

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

GND

CE

OE

WE

V

CC

24-PIN ENCAPSULATED PACKAGE

720 MIL EXTENDED

PIN DESCRIPTION

A

0

-A

10

– Address Inputs

DQ

0

-DQ

7

– Data In/Data Out

CE

– Chip Enable

WE

– Write Enable

OE

– Output Enable

V

CC

– Power (+5V)

GND

– Ground

DESCRIPTION

The DS1220AB and DS1220AD are 16,384-bit, fully
static, nonvolatile SRAMs organized as 2048 words by
8 bits. Each NV SRAM has a self-contained lithium en-
ergy source and control circuitry which constantly moni-
tors V

CC

for an out-of-tolerance condition. When such a

condition occurs, the lithium energy source automati-
cally switches on and write protection is unconditionally
enabled to prevent data corruption. The NV SRAMs can

be used in place of existing 2K x 8 SRAMs directly con-
forming to the popular bytewide 24-pin DIP standard.
The devices also match the pinout of the 2716 EPROM
and the 2816 EEPROM, allowing direct substitution
while enhancing performance. There is no limit on the
number of write cycles that can be executed and no ad-
ditional support circuitry is required for microprocessor
interfacing.

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