Rainbow Electronics ADC08200 - Manual (Page 17)

Applications Information
(Continued)
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncom-
mon for high speed digital circuits (e.g., 74F and 74AC
devices) to exhibit undershoot that goes more than a volt
below ground. A 51
Ω resistor in series with the offending
digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC08200. Such practice may lead to conversion inaccura-
cies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is
required from V
DR
and DR GND. These large charging cur-
rent spikes can couple into the analog section, degrading
dynamic performance. Buffering the digital data outputs (with
a 74AF541, for example) may be necessary if the data bus
capacitance exceeds 5 pF. Dynamic performance can also
be improved by adding 100
Ω series resistors at each digital
output, reducing the energy coupled back into the converter
input pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the
input alternates between 3 pF and 4 pF with the clock. This
dynamic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device.
Driving the V
RT
pin or the V
RB
pin with devices that can
not source or sink the current required by the ladder. As
mentioned in Section 1.0, care should be taken to see that
any driving devices can source sufficient current into the V
RT
pin and sink sufficient current from the V
RB
pin. If these pins
are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.
Using a clock source with excessive jitter, using an
excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. The use of simple
gates with RC timing is generally inadequate as a clock
source.
ADC08200
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