Rainbow Electronics DS2141A User Manual
Page 27
DS2141A
021997 27/35
TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED)
TCLK
TSER
1
TPOS,
TNEG
1
TSYNC
2
TSYNC
3
TCHCLK
CHANNEL 2
LSB MSB
LSB
MSB
F
CHANNEL 1
LSB MSB
CHANNEL 1
LSB
MSB
LSB MSB
CHANNEL 24
F
CHANNEL 23
TCHBLK
4
TLCLK
TLINK
Don’t Care
NOTES:
1. There is a 10 TCLK delay from TSER to TPOS, TNEG.
2. TSYNC is in the input mode (TCR2.2=0).
3. TSYNC is in the output mode (TCR2.2=1).
4. TCHBLK is programmed to block Channel 1.
LINE INTERFACE CONTROL TIMING
LI_CS
LI_SCLK
LI_SDI
1
LI_SDI
2
0
0
0
0
0
0
0
CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7
CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7
0
0
0
0
0
1
1
0
1
324 ns
324 ns
324 ns
NOTES:
1. A write to CRB1 will cause the DS2141A to output this sequence.
2. A write to CRB2 will cause the DS2141A to output this sequence.
3. Timing numbers are based on RCLK=1.544 MHz with 50% duty cycle.