Rainbow Electronics AT89C5122 User Manual
Page 52
52
AT8xC5122/23
4202E–SCR–06/06
Reset Value = XXXX XXX0b
Reset Value = 0000 0000b
Reset Value = 0000 0000b
Table 27. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
SPIX2
Bit Number Bit Mnemonic Description
7 - 4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
SPIX2
SPI clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Cleared to bypass the PR1 prescaler.
Set to select the PR1 output for this peripheral.
Table 28. PLL Control Register - PLLCON (S:A3h)
7
6
5
4
3
2
1
0
-
-
-
-
-
EXT48
PLLEN PLOCK
Bit Number Bit Mnemonic Description
7 - 3
-
Reserved
The value read from these bits is always 0. Do not set this bits.
2
EXT48
External 48 MHz Enable Bit
Set this bit to select XTAL1 as USB clock.
Clear this bit to select PLL as USB clock.
SCIB clock is controlled by EXT48 bit and XTSCS bit.
1
PLLEN
PLL Enable bit
Set to enable the PLL.
Clear to disable the PLL.
0
PLOCK
PLL Lock Indicator
Set by hardware when PLL is locked
Clear by hardware when PLL is unlocked
Table 29. PLL Divider Register - PLLDIV (S:A4h)
7
6
5
4
3
2
1
0
R3
R2
R1
R0
N3
N2
N1 N0
Bit Number Bit Mnemonic Description
7 - 4
R3:0
PLL R Divider Bits
3 - 0
N3:0
PLL N Divider Bits