Rainbow Electronics DS3904 - Manual (Page 10)

DS3904
DS3904 Triple 128-Position Nonvolatile
Variable Digital Resistor/Switch
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master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line high to enable the master to
generate the stop condition.
Data transfer from a master transmitter to a slave
receiver.
The first byte transmitted by the master is the
command/control byte. Next follows a number of data
bytes. The slave returns an acknowledge bit after each
received byte.
Data transfer from a slave transmitter to a master
receiver.
The master transmits the first byte (the com-
mand/control byte) to the slave. The slave then returns
an acknowledge bit. Next follows the data byte trans-
mitted by the slave to the master. The master returns
NACK followed by a stop.
The master device generates all serial clock pulses and
the start and stop conditions. A transfer is ended with a
stop condition or with a repeated start condition. Since
a repeated start condition is also the beginning of the
next serial transfer, the bus is not released.
The DS3904 can operate in the following three modes:
1) Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address
recognition is performed by hardware after the
slave (device) address and direction bit has been
received.
2) Slave Transmitter Mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode the direction bit indicates
that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS3904 while the serial
clock is input on SCL. Start and stop conditions are
recognized as the beginning and end of a serial
transfer.
3) Slave Address: Command/control byte is the first
byte received following the start condition from the
master device. The command/control byte consists
of a 6-bit control code. For the DS3904, this is set
as 101000 binary for read/write operations. The
next bit of the command/control byte is the device
select bit or slave address (A0). It is used by the
master device to select which of two devices is to
be accessed. When reading or writing the DS3904,
the device-select bits must match the device-select
pin (A0). The last bit of the command/control byte
(R/W) defines the operation to be performed. When
set to a ‘1’, a read operation is selected, and when
set to a ‘0’, a write operation is selected.
1
MSB
START
LSB
COMMAND BYTE
DEVICE IDENTIFIER
OR
"FAMILY CODE"
SLAVE
ADDRESS
0 1 0 0 0 A0 R/W
MSB LSB
DATA BYTE
RHIZ
CONTROL BIT
RESISTOR SETTING
Figure 4. Command and Data Byte Structures
MSB LSB
1 0 0 1 0 0 0 START
MSB LSB
1 1 1 ACK ACK 1 1 0 0 0
MSB LSB
0 1 0 0 1 0 0 1 START
MSB LSB
1 1 1 ACK STOP ACK 1 1 0 0 1
MSB LSB
0 1 0 0 1 0 0 0 START
MSB LSB
1 1 1 ACK
STOP
ACK 1 1 0 1 0
MSB LSB
1 0 0 1 0 0 1 START
MSB LSB
1 1 1 ACK ACK 1 1 0 0 1
READ DATA FROM
RESISTOR 1 (F9h)
WITH A0 = 1
WRITE 55h TO
RESISTOR 0 (F8h)
WITH A0 = 0
MSB LSB
1 0 0 1 0 0 1
REPEATED
START
MSB LSB
ACK STOP NACK
FROM
SLAVE FROM
SLAVE FROM
SLAVE
MASTER
0
0
1
STOP
MSB LSB
0 1 0 ACK 1 0 1 0 1
MSB LSB
1 0 0 ACK 0 0 0 0 0
MSB LSB
0 1 1 ACK 1 1 1 1 1
WRITE 80h (Hi-Z) TO
RESISTOR 1 (F9h)
WITH A0 = 1
WRITE 7Fh TO
RESISTOR 2 (FAh)
WITH A0 = 0
EXAMPLE 2-WIRE TRANSACTIONS
RESISTOR DATA
Figure 5. Example 2-Wire Transactions