Rainbow Electronics DS2165Q User Manual
Page 6
DS2165/DS2165Q
041295 6/17
INPUT TIME SLOT REGISTER Figure 5
(MSB)
(LSB)
–
–
D5
D4
D3
D2
D1
D0
SYMBOL
POSITION
NAME AND DESCRIPTION
-
ITR.7
Reserved; must be 0 for proper operation.
-
ITR.6
Reserved; must be 0 for proper operation.
D5
ITR.5
MSB of input time slot register.
D4
ITR.4
D3
ITR.3
D2
ITR.2
D1
ITR.1
D0
ITR.0
LSB of input time slot register.
OUTPUT TIME SLOT REGISTER Figure 6
(MSB)
(LSB)
–
–
D5
D4
D3
D2
D1
D0
SYMBOL
POSITION
NAME AND DESCRIPTION
-
OTR.7
Reserved; must be 0 for proper operation.
-
OTR.6
Reserved; must be 0 for proper operation.
D5
OTR.5
MSB of output time slot register.
D4
OTR.4
D3
OTR.3
D2
OTR.2
D1
OTR.1
D0
OTR.0
LSB of output time slot register.
TIME SLOT ASSIGNMENT/ORGANIZATION
Onboard counters establish when PCM and ADPCM
I/O occurs. The counters are programmed via the time
slot registers. Time slot size (number of bits wide) is de-
termined by the state of CP/EX. The number of time
slots available is determined by both the state of CP/EX
and U/A. (See Figures 7 through 10.) For example, if the
X channel is set to compress (CP/EX = 1) and it is set to
expect
µ
-law data (U/A = 1), then the input port (XIN) is
set up for 32 8-bit time slots and the output port (XOUT)
is set up for 64 4-bit time slots. The time slot organiza-
tion is not dependent on which algorithm has been se-
lected. NOTE: Time slots are counted from the frame
sync signal starting at the first rising edge of either CLKX
or CLKY after the frame sync.