Figure 7-33. clear status latched register on read, Figure 7-33, Figure 7-34 – Rainbow Electronics DS3170 User Manual
Page 49
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DS3170 DS3/E3 Single-Chip Transceiver
49 of 233
Figure 7-33. Clear Status Latched Register on Read
D[15:0]
A[10:1]
A[0]/BSWAP
0x1C0
0xFFFF
0x1C0
0x0000
Z
Z
Z
Z
RD
WR
CS
RDY
Figure 7-34. Clear Status Latched Register on Write
D[15:0]
A[10:1]
A[0]/BSWAP
0x1C0
0xFFFF
0x1C0
0x5555
0x1C0
0xAAAA
Z
Z
Z
Z
Z
Z
RD
WR
CS
RDY
and
show exaggerated views of the Ready Signal to describe the difference in access
times to write or read to or from various memory locations on the DS3170 device. Some registers will have a faster
access time than others and if needed, the user can implement the RDY signal to maximize efficiency of read and
write accesses.
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