Rainbow Electronics ATmega163L - Manual (Page 64)

ATmega163(L)
64
The FE bit is cleared when the stop bit of received data is one.
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Bit 3 - OR: OverRun
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read
before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will
be set once the valid data still in UDR is read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
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Bit 2 - Res: Reserved Bit
This bit is a reserved bit in the ATmega163 and will always read as zero.
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Bits 1 - U2X: Double the UART Transmission Speed
Setting this bit will reduce the division of the baud rate generator clock from 16 to 8, effectively doubling the transfer speed
at the expense of robustness. For a detailed description, see “Double Speed Transmission” on page 66.
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Bit 0 - MPCM: Multi-processor Communication Mode
This bit is used to enter Multi-Processor Communication Mode. The bit is set when the slave MCU waits for an address
byte to be received. When the MCU has been addressed, the MCU switches off the MPCM bit, and starts data reception.
For a detailed description, see “Multi-processor Communication Mode” on page 62.
UART Control and Status Register B - UCSRB
• Bit 7 - RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed
provided that global interrupts are enabled.
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Bit 6 - TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed
provided that global interrupts are enabled.
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Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be
executed provided that global interrupts are enabled.
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Bit 4 - RXEN: Receiver Enable
This bit enables the UART receiver when set (one). When the receiver is disabled, the RXC, OR, and FE status flags can-
not become set. If these flags are set, turning off RXEN does not cause them to be cleared.
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Bit 3 - TXEN: Transmitter Enable
This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the
transmitter is not disabled before the character in the shift register plus any following character in UDR has been com-
pletely transmitted.
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Bit 2 - CHR9: 9 Bit Characters
When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is read and
written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity
bit.
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Bit 1 - RXB8: Receive Data Bit 8
When CHR9 is set (one), RXB8 is the 9th data bit of the received character.
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Bit 0 - TXB8: Transmit Data Bit 8
When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.
Bit 7 6 5 4 3 2 1 0
$0A ($2A) RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 UCSRB
Read/Write R/W R/W R/W R/W R/W R/W R W
Initial value 0 0 0 0 0 0 1 0