Document Outline

• Features
• Description
• Pin Configuration
• Pin Description: RF Part
• Pin Description: Microcontroller Part 
• UHF ASK/FSK Transmitter Block
• Features
• Description
• General Description
• Functional Description
  • ASK Transmission
  • FSK Transmission
  • CLK Output
    • Clock Pulse Take Over
    • Output Matching and Power Setting
  • Application Circuit
• Absolute Maximum Ratings
• Thermal Resistance
• Electrical Characteristics
• Microcontroller Block
• Features
• Description
• Introduction
• MARC4 Architecture General Description
• Components of MARC4 Core
  • ROM
  • RAM
    • Expression Stack
    • Return Stack
  • Registers
    • Program Counter (PC)
    • RAM Address Registers
    • Expression Stack Pointer (SP)
    • Return Stack Pointer (RP)
    • RAM Address Registers (X and Y)
    • Top of Stack (TOS)
    • Condition Code Register (CCR)
    • Carry/Borrow (C)
    • Branch (B)
    • Interrupt Enable (I)
  • ALU
  • I/O Bus
  • Instruction Set
  • Interrupt Structure
    • Interrupt Processing
    • Interrupt Latency
  • Software Interrupts
  • Hardware Interrupts
• Master Reset
  • Power-on Reset and Brown-out Detection
    • Watchdog Reset
    • External Clock Supervisor
• Voltage Monitor
  • Voltage Monitor Control/ Status Register
• Clock Generation
  • Clock Module
  • Oscillator Circuits and External Clock Input Stage
    • RC-oscillator 1 Fully Integrated
    • External Input Clock
    • RC-oscillator 2 with External Trimming Resistor
    • 4-MHz Oscillator
    • 32-kHz Oscillator
  • Clock Management
    • Clock Management Register (CM)
    • System Configuration Register (SC)
• Power-down Modes
• Peripheral Modules
  • Addressing Peripherals
• Bi-directional Ports
  • Bi-directional Port 1
  • Bi-directional Port 2
    • Port 2 Data Register (P2DAT)
    • Port 2 Control Register (P2CR)
  • Bi-directional Port 5
    • Port 5 Data Register (P5DAT)
    • Port 5 Control Register (P5CR) Byte Write
  • Bi-directional Port 4
    • Port 4 Data Register (P4DAT)
    • Port 4 Control Register (P4CR) Byte Write
  • Bi-directional Port 6
    • Port 6 Data Register (P6DAT)
    • Port 6 Control Register (P6CR)
  • Universal Timer/Counter/ Communication Module (UTCM)
  • Timer 1
    • Timer 1 Control Register 1 (T1C1)
    • Timer 1 Control Register 2 (T1C2)
    • Watchdog Control Register (WDC)
  • Timer 2
  • Timer 2 Modes
    • Mode 1: 12-bit Compare Counter
    • Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler
    • Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler
  • Timer 2 Output Modes
  • Timer 2 Output Signals
    • Timer 2 Output Mode 1
    • Timer 2 Output Mode 2
    • Timer 2 Output Mode 3
    • Timer 2 Output Mode 4
    • Timer 2 Output Mode 5
    • Timer 2 Output Mode 7
  • Timer 2 Registers
    • Timer 2 Control Register (T2C)
    • Timer 2 Mode Register 1 (T2M1)
    • Duty Cycle Generator
    • Timer 2 Mode Register 2 (T2M2)
    • Timer 2 Compare and Compare Mode Registers
    • Timer 2 Compare Mode Register (T2CM)
    • Timer 2 COmpare Register 1 (T2CO1)
    • Timer 2 COmpare Register 2 (T2CO2) Byte Write
• Timer 3
  • Features
  • Timer/Counter Modes
    • Timer 3 – Mode 1: Timer/Counter
    • Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
    • Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)
    • Timer 3 – Mode 4: Timer/Counter
    • Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
  • Timer 3 Modulator/Demodulator Modes
    • Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle Flip- Fl...
    • Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
    • Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
    • Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
    • Timer 3 – Mode 10: Manchester Demodulation/ Pulse-width Demodulation
    • Timer 3 – Mode 11: Biphase Demodulation
    • Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
  • Timer 3 Modulator for Carrier Frequency Burst Modulation
  • Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
  • Timer 3 Registers
    • Timer 3 Mode Register (T3M)
    • Timer 3 Control Register 1 (T3C) Write
    • Timer 3 Status Register 1 (T3ST) Read
    • Timer 3 Clock Select Register (T3CS)
    • Timer 3 Compare- and Compare-mode Register
    • Timer 3 Compare-Mode Register 1 (T3CM1)
    • Timer 3 Compare Mode Register 2 (T3CM2)
    • Timer 3 COmpare Register 1 (T3CO1) Byte Write
    • Timer 3 COmpare Register 2 (T3CO2) Byte Write
  • Timer 3 Capture Register
    • Timer 3 CaPture Register (T3CP) Byte Read
  • Synchronous Serial Interface (SSI)
    • SSI Peripheral Configuration
    • General SSI Operation
    • 8-bit Synchronous Mode
    • 9-bit Shift Mode (MCL)
    • 8-bit Pseudo MCL Mode
    • MCL Bus Protocol
    • SSI Interrupt
    • Modulation and Demodulation
    • Internal 2-wire Multi-chip Link
  • Serial Interface Registers
    • Serial Interface Control Register 1 (SIC1)
    • Serial Interface Control Register 2 (SIC2)
    • Serial Interface Status and Control Register (SISC)
    • Serial Transmit Buffer (STB) – Byte Write
    • Serial Receive Buffer (SRB) – Byte Read
• Combination Modes
  • Combination Mode Timer 2 and SSI
    • Combination Mode 1: Burst Modulation
    • Combination Mode 2: Biphase Modulation 1
    • Combination Mode 3: Manchester Modulation 1
    • Combination Mode 4: Manchester Modulation 2
    • Combination Mode 5: Biphase Modulation 2
  • Combination Mode Timer 3 and SSI
    • Combination Mode 6: FSK Modulation
    • Combination Mode 7: Pulse-width Modulation (PWM)
    • Combination Mode 8: Manchester Demodulation/ Pulse-width Demodulation
    • Combination Mode 9: Biphase Demodulation
  • Combination Mode Timer 2 and Timer 3
    • Combination Mode 10: Frequency Measurement or Event Counter with Time Gate
    • Combination Mode 11: Burst Modulation 1
  • Combination Mode Timer 2, Timer 3 and SSI
    • Combination Mode 12: Burst Modulation 2
    • Combination Mode 13: FSK Modulation
• Microcontroller Block
  • Internal 2-wire Multi-chip Link
  • U505M EEPROM
  • Serial Interface
    • Serial Protocol
    • Control Byte Format
  • EEPROM
    • EEPROM – Operating Modes
    • Write Operations
    • Acknowledge Polling
    • Write One Data Byte
    • Write Two Data Bytes
    • Write Control Byte Only
    • Write Control Bytes
    • Read Operations
    • Read One Data Byte
    • Read Two Data Bytes
    • Read n Data Bytes
    • Read Control Bytes
  • Initialization After a Reset Condition
• Absolute Maximum Ratings
• Thermal Resistance
• DC Operating Characteristics
• AC Characteristics
• Crystal Characteristics
• Ordering Information
• Ordering Information
• Package Information
• Table of Contents